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    • 3. 发明授权
    • System and method for arbitrating between memory access requests
    • 在内存访问请求之间进行仲裁的系统和方法
    • US08171187B2
    • 2012-05-01
    • US12179799
    • 2008-07-25
    • Anton RozenRoman MostinskiMichael PrielLeonid Smolyansky
    • Anton RozenRoman MostinskiMichael PrielLeonid Smolyansky
    • G06F3/00
    • G06F13/1605Y02D10/14
    • A system having memory access capabilities, the system includes: (i) a dynamic voltage and frequency scaling (DVFS) controller, adapted to determine a level of a voltage supply supplied to a first memory access requester and a frequency of a clock signal provided to the first memory access requester and to generate a DVFS indication that is indicative of the determination; (ii) a hardware access request determination module, adapted to determine a priority of memory access request issued by the first memory access requester in response to the DVFS indication; and (iii) a direct memory access arbitrator, adapted to arbitrate between memory access requests issued by the first memory access requester and another memory access requester in response to priorities associated with the memory access requests.
    • 一种具有存储器访问能力的系统,该系统包括:(i)动态电压和频率缩放(DVFS)控制器,适于确定提供给第一存储器访问请求者的电压电平的电平和提供给 所述第一存储器访问请求器并且生成指示所述确定的DVFS指示; (ii)硬件访问请求确定模块,用于响应于所述DVFS指示确定由所述第一存储器访问请求者发出的存储器访问请求的优先级; 以及(iii)直接存储器访问仲裁器,适于响应于与所述存储器访问请求相关联的优先级,在由所述第一存储器访问请求者发出的存储器访问请求与另一存储器访问请求者之间进行仲裁。
    • 7. 发明申请
    • System and Method For Storing State Information
    • 用于存储状态信息的系统和方法
    • US20080256551A1
    • 2008-10-16
    • US12067587
    • 2005-09-21
    • Michael PrielDan KuzminLeonid Smolyansky
    • Michael PrielDan KuzminLeonid Smolyansky
    • G06F9/46
    • G06F9/462
    • A method for storing state information, the method includes storing, at a first circuit, state information representative of a state of a second circuit while the second circuit enters a low power mode; characterized by receiving an indication that a task switching from a first task to a second task should occur; storing a state information representative of a state of the second circuit, at the first circuit; receiving an indication that the first task should be resumed; and writing the stored state information from the first circuit to the second circuit. A system includes a first circuit and a second circuit, whereas the first circuit is connected to the second circuit and is adapted to store state information representative of a state of a second circuit; characterized by including a controller adapted to control a storage of the state information if at least a portion of the second circuit is powered down or if the second circuit is associated with a task switching operation.
    • 一种用于存储状态信息的方法,所述方法包括在第一电路处存储表示第二电路的状态的状态信息,同时第二电路进入低功率模式; 其特征在于接收从第一任务切换到第二任务的任务应发生的指示; 在所述第一电路处存储表示所述第二电路的状态的状态信息; 收到第一个任务应恢复的指示; 以及将所存储的状态信息从第一电路写入第二电路。 一种系统包括第一电路和第二电路,而第一电路连接到第二电路,并适于存储表示第二电路的状态的状态信息; 其特征在于包括控制器,其适于在所述第二电路的至少一部分断电或者所述第二电路与任务切换操作相关联时控制所述状态信息的存储。
    • 9. 发明授权
    • Integrated circuit and method for reducing violations of a timing constraint
    • 用于减少违反定时约束的集成电路和方法
    • US08706928B2
    • 2014-04-22
    • US13504737
    • 2009-11-26
    • Roman MostinskiLavi KochLeonid Smolyansky
    • Roman MostinskiLavi KochLeonid Smolyansky
    • G06F3/00G06F5/00
    • G06F13/1673G06F13/1605
    • An integrated circuit comprises a shared resource for providing data to a buffer. The buffer is coupled to a buffer level monitor and a filling circuit. An access-requesting circuit is coupled to the shared resource for receiving the data from the shared resource when the access-requesting circuit has access to the shared resource. An arbiter is coupled to the shared resource, the filling circuit, and the access-requesting circuit, for receiving access requests from the filling circuit and from the access-requesting circuit, and for granting to a selected one thereof access to the shared resource. A controller is coupled to the buffer level monitor and to the access-requesting circuit, for causing the access-requesting circuit to reduce a rate of access requests sent to the arbiter when a condition involving the monitored level of data in the buffer indicates an anticipated violation of a timing constraint.
    • 集成电路包括用于向缓冲器提供数据的共享资源。 缓冲器耦合到缓冲液位监视器和充电电路。 访问请求电路耦合到共享资源,用于当访问请求电路访问共享资源时从共享资源接收数据。 仲裁器耦合到共享资源,填充电路和访问请求电路,用于从填充电路和访问请求电路接收访问请求,并且向所选共享资源授予对共享资源的访问权限。 控制器耦合到缓冲器级监视器和访问请求电路,用于当涉及缓冲器中监视的数据级别的条件指示预期时,访问请求电路降低发送到仲裁器的访问请求的速率 违反时间限制。