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11. 发明授权

US06350559B1 Method for creating thinner resist coating that also has fewer pinholes 有权
标题翻译：创造也具有较少针孔的较薄抗蚀剂涂层的方法
公开(公告)号：US06350559B1
公开(公告)日：2002-02-26
申请号：US09398642
申请日：1999-09-17
申请人： Michael K. Templeton , Kathleen R. Early , Christopher F. Lyons
发明人： Michael K. Templeton , Kathleen R. Early , Christopher F. Lyons
IPC分类号： G03F700
CPC分类号： H01L21/312 , G03F7/168
摘要： In one embodiment, the present invention relates to a method of forming a thin photoresist layer having a low defect density, involving the steps of depositing a photoresist layer having a thickness from greater than about 0.5 &mgr;m to about 2 &mgr;m on a semiconductor substrate; and removing at least a portion of the photoresist layer to provide the thin photoresist layer having the low defect density and a thickness from about 0.1 &mgr;m to about 0.5 &mgr;m. In another embodiment, the present invention relates to a method of reducing pinhole defects in a thin photoresist layer having a thickness below about 0.5 &mgr;m comprising a photoresist material, involving the steps of depositing a layer of the photoresist material having a thickness greater than about 0.5 &mgr;m; and etching at least a portion of the photoresist material to provide the thin photoresist layer having the thickness below about 0.5 &mgr;m, wherein the thickness of the thin photoresist layer is about 90% or less than the thickness of the layer of the photoresist material.
摘要翻译：在一个实施方案中，本发明涉及一种形成具有低缺陷密度的薄的光致抗蚀剂层的方法，包括以下步骤：在半导体衬底上沉积厚度大于约0.5μm至约2μm的光致抗蚀剂层; 以及去除所述光致抗蚀剂层的至少一部分以提供具有低缺陷密度和约0.1μm至约0.5μm的厚度的薄光致抗蚀剂层。在另一个实施方案中，本发明涉及一种减少厚度低于约0.5μm的光致抗蚀剂薄层中的针孔缺陷的方法，该光致抗蚀剂层包括光致抗蚀剂材料，其包括以下步骤：沉积厚度大于约0.5μm的光致抗蚀剂材料层妈妈并蚀刻所述光致抗蚀剂材料的至少一部分以提供具有低于约0.5μm厚度的薄的光致抗蚀剂层，其中所述光致抗蚀剂层的厚度为所述光致抗蚀剂材料层的厚度的约90％或更小。

12. 发明授权

US06214737B1 Simplified sidewall formation for sidewall patterning of sub 100 nm structures 失效
标题翻译：亚100 nm结构的侧壁图案的简化侧壁形成
公开(公告)号：US06214737B1
公开(公告)日：2001-04-10
申请号：US09234379
申请日：1999-01-20
申请人： Christopher F. Lyons , Michael K. Templeton , Kathleen R. Early
发明人： Christopher F. Lyons , Michael K. Templeton , Kathleen R. Early
IPC分类号： H01L213065
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/32139 , H01L21/76838
摘要： In one embodiment, the present invention relates to a method of forming a conductive structure having a width of about 100 nm or less, involving the steps of providing a substrate having a conductive film; patterning a mask over a first portion of the conductive film wherein a second portion of the conductive film is exposed; partially etching the second portion of the conductive film thereby forming a sidewall in the conductive film; removing the mask; depositing a sidewall film over the conductive film, the sidewall film having a vertical portion adjacent the sidewall of the conductive film and a horizontal portion in areas not adjacent the sidewall of the conductive film; removing the horizontal portion of the sidewall film exposing a third portion of the conductive film; and etching the third portion of the conductive film thereby providing the conductive structure having a width of about 100 nm or less underlying the vertical portion of the sidewall film.
摘要翻译：在一个实施例中，本发明涉及一种形成宽度为约100nm或更小的导电结构的方法，包括提供具有导电膜的基板的步骤; 在导电膜的第一部分上图案化掩模，其中导电膜的第二部分被暴露; 部分蚀刻导电膜的第二部分，从而在导电膜中形成侧壁; 去除面膜; 在所述导电膜上沉积侧壁膜，所述侧壁膜具有邻近所述导电膜的侧壁的垂直部分和在不邻近所述导电膜的侧壁的区域中的水平部分; 去除暴露导电膜的第三部分的侧壁膜的水平部分; 并且蚀刻导电膜的第三部分，从而提供具有在侧壁膜的垂直部分下方的约100nm或更小的宽度的导电结构。

13. 发明授权

US6030868A Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation 失效
标题翻译：通过多晶硅氧化隔离相邻位线上的浮栅，消除氧氮化物（ONO）蚀刻残渣和多晶硅桁架
公开(公告)号：US6030868A
公开(公告)日：2000-02-29
申请号：US33916
申请日：1998-03-03
申请人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan , Mark T. Ramsbey
发明人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan , Mark T. Ramsbey
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for fabricating a first memory cell and a second memory cell having floating gates electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate, portions of the poly I layer to serve as future floating gates for the first and second memory cells. An interpoly dielectric layer is formed over the poly I layer. At least a portion of the interpoly dielectric layer is etched to expose at least a portion of the poly I layer so as to pattern the floating gates on either side of the exposed portion of the poly I layer. The exposed portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. A second polysilicon (poly II) layer is formed substantially free of abrupt changes in step height.
摘要翻译：一种制造第一存储单元的方法和具有彼此电隔离的浮动栅极的第二存储单元。在氧化物涂覆的基底上形成第一多晶硅（poly I）层，多晶硅层的部分用作第一和第二存储单元的未来浮动栅极。在多晶硅层上形成多层介电层。蚀刻至少一部分互电介质层以暴露多晶硅层的至少一部分，以便在多晶硅层的暴露部分的任一侧上对浮动栅极进行图案化。多层I的暴露部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮动栅极与第二存储单元的浮置栅极电隔离。形成基本上没有台阶高度突然变化的第二多晶硅（poly II）层。

14. 发明授权

US07153364B1 Re-circulation and reuse of dummy-dispensed resist 失效
标题翻译：虚拟分配抗蚀剂的再循环和再利用
公开(公告)号：US07153364B1
公开(公告)日：2006-12-26
申请号：US10000208
申请日：2001-10-23
申请人： Bharath Rangarajan , Ramkumar Subramanian , Khoi A. Phan , Ursula Q. Quinto , Michael K. Templeton
发明人： Bharath Rangarajan , Ramkumar Subramanian , Khoi A. Phan , Ursula Q. Quinto , Michael K. Templeton
IPC分类号： B05B1/28 , B05B15/04 , B05B3/00
CPC分类号： H01L21/6715 , B05B15/50 , B05C11/08
摘要： The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.
摘要翻译：本发明提供了一种用于分配头的虚拟分配抗蚀剂的系统和方法，同时减轻与虚拟分配过程相关的废物。虚拟分配的抗蚀剂返回到被采集的储存器。在基板应用之间，分配头可以被定位成将抗蚀剂分配到返回线中。来自分配头的抗蚀剂的流动在分配头保持抗干燥。通过将虚拟分配的抗蚀剂漏出到具有低体积的返回管线中，例如，可以减轻来自虚拟分配过程的废物。

15. 发明授权

US07145653B1 In situ particle monitoring for defect reduction 有权
标题翻译：用于缺陷减少的原位粒子监测
公开(公告)号：US07145653B1
公开(公告)日：2006-12-05
申请号：US09591017
申请日：2000-06-09
申请人： Michael K. Templeton , Bharath Rangarajan
发明人： Michael K. Templeton , Bharath Rangarajan
IPC分类号： G01N21/00
CPC分类号： G01N21/5907 , G01N15/0205 , G01N21/94 , G01N21/9501 , G01N2021/5961 , G01N2021/8411 , H01L22/10
摘要： A system and method is provided for monitoring and controlling the contaminant particle count contained in an aerosol during a photoresist coating and/or development process of a semiconductor. The monitoring system monitors the contaminate particle count present in the environment of the photoresist coating and/or development process, such as in a process chamber or a cup, enclosing the wafer during the process. The present invention employs in situ laser scattering or laser doppler anemometry techniques to detect the particle count level in the chamber or cup. A plurality of lasers and detectors can be positioned at different heights in or outside of a chamber or cup to facilitate detecting particles at different height levels. A laser could be used in conjunction with mirrors to provide a similar measurement. The particle count level can be used to compare with the defect level, so that it can be determined if a cleaner environment and/or process should be implemented.
摘要翻译：提供了一种系统和方法，用于在半导体的光致抗蚀剂涂覆和/或显影过程期间监测和控制包含在气溶胶中的污染物颗粒数。监测系统监测光致抗蚀剂涂层和/或显影过程环境中存在的污染颗粒数，例如在处理室或杯中，在处理过程中包围晶片。本发明采用原位激光散射或激光多普勒血流计技术来检测腔室或杯子中的颗粒计数水平。多个激光器和检测器可以位于室或杯内或室外的不同高度处，以便于检测不同高度水平的颗粒。激光可以与镜子一起使用以提供类似的测量。可以使用粒子计数水平与缺陷水平进行比较，以便可以确定是否应实施更清洁的环境和/或过程。

16. 发明授权

US07078348B1 Dual layer patterning scheme to make dual damascene 失效
标题翻译：双层图案方案制作双镶嵌
公开(公告)号：US07078348B1
公开(公告)日：2006-07-18
申请号：US09893188
申请日：2001-06-27
申请人： Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan , Michael K. Templeton
发明人： Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan , Michael K. Templeton
IPC分类号： H01L21/302 , H01L21/3065
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76811 , H01L21/76813
摘要： One aspect of the present invention relates to a method for making a dual damascene pattern in an insulative layer in a single etch process involving providing a wafer having at least one insulative layer formed thereon; depositing a first photoresist layer over the at least one insulative layer; patterning a first image into the first photoresist layer; curing the first patterned photoresist layer; depositing a second photoresist layer over the first patterned photoresist layer; patterning a second image into the second photoresist layer; and etching the at least one insulative layer through the first patterned photoresist layer and the second patterned photoresist layer simultaneously in the single etch process.
摘要翻译：本发明的一个方面涉及在单一蚀刻工艺中在绝缘层中制造双镶嵌图案的方法，该方法包括提供其上形成有至少一个绝缘层的晶片; 在所述至少一个绝缘层上沉积第一光致抗蚀剂层; 将第一图像图案化成第一光致抗蚀剂层; 固化第一图案化光致抗蚀剂层; 在所述第一图案化光致抗蚀剂层上沉积第二光致抗蚀剂层; 将第二图像图案化成第二光致抗蚀剂层; 以及在单次蚀刻工艺中同时蚀刻通过第一图案化光致抗蚀剂层和第二图案化光致抗蚀剂层的至少一个绝缘层。

17. 发明授权

US06746822B1 Use of surface coupling agent to improve adhesion 有权
标题翻译：使用表面偶联剂改善附着力
公开(公告)号：US06746822B1
公开(公告)日：2004-06-08
申请号：US10050484
申请日：2002-01-16
申请人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh
发明人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh
IPC分类号： G03F720
CPC分类号： G03F7/265 , H01L21/0273 , H01L21/31144 , H01L21/32139
摘要： Disclosed are methods of processing a semiconductor structure, involving the steps of depositing a light-degradable surface coupling agent on a semiconductor substrate; depositing a resist over the light-degradable surface coupling agent; irradiating portions of the resist, wherein the light-degradable surface coupling agent under the irradiated portions of the resist at least partially decomposes; and developing the resist.
摘要翻译：公开了处理半导体结构的方法，包括在半导体衬底上沉积可光降解的表面偶联剂的步骤; 在光可降解表面偶联剂上沉积抗蚀剂; 照射抗蚀剂的部分，其中抗蚀剂照射部分下的可光降解表面偶联剂至少部分分解; 并开发抗蚀剂。

18. 发明授权

US06629786B1 Active control of developer time and temperature 失效
标题翻译：主动控制显影时间和温度
公开(公告)号：US06629786B1
公开(公告)日：2003-10-07
申请号：US09845232
申请日：2001-04-30
申请人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Ramkumar Subramanian
发明人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G03D500
CPC分类号： G03D5/00
摘要： A system for regulating the time and temperature of a development process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being developed on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the progress of development of the respective portions of the wafer. The measuring system provides progress of development related data to a processor that determines the progress of development of the respective portions of the wafer. The system also includes a plurality of heating devices, each heating device corresponds to a respective portion of the developer and provides for the heating thereof. The processor selectively controls the heating devices so as to regulate temperature of the respective portions of the wafer.
摘要翻译：提供了一种用于调节开发过程的时间和温度的系统。该系统包括一个或多个光源，每个光源将光引导到在晶片上显影的一个或多个光栅。从光栅反射的光被测量系统收集，该系统处理收集的光。通过光栅的光可以类似地由处理所收集的光的测量系统收集。所收集的光表示晶片的各个部分的显影进展。该测量系统提供开发相关数据的进展到处理器，该处理器确定晶片的相应部分的开发进度。该系统还包括多个加热装置，每个加热装置对应于显影剂的相应部分并提供其加热。处理器选择性地控制加热装置，以调节晶片各部分的温度。

19. 发明授权

US06556303B1 Scattered signal collection using strobed technique 有权
标题翻译：使用频闪技术分散信号采集
公开(公告)号：US06556303B1
公开(公告)日：2003-04-29
申请号：US09902366
申请日：2001-07-10
申请人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Khoi A. Phan
发明人： Bharath Rangarajan , Michael K. Templeton , Bhanwar Singh , Khoi A. Phan
IPC分类号： G01B1114
CPC分类号： G01B11/0683 , G01B11/0625 , H01L22/12
摘要： The present invention is directed to a system and a method for controlling a thin film formation on a moving substrate as part of a process for manufacturing an integrated circuit. The invention involves the use of scatterometry to control the thin film formation process by analyzing the thin film on the moving substrate in a periodic manner. A registration feature associated with the moving substrate can be utilized in conjunction with a signaling system to determine a position of the moving substrate, whereby a repeatable analysis of a corresponding location on the moving substrate can be performed. Scatterometry permits in-situ measurements of thin film formation progress, whereby thin film formation process conditions can be controlled in a feedback loop to obtain a targeted result. Scatterometry can also be facilitated by providing a grating pattern on a non-production portion of the substrate.
摘要翻译：本发明涉及一种用于控制移动衬底上的薄膜形成的系统和方法，作为用于制造集成电路的工艺的一部分。本发明涉及使用散射法来以周期性方式分析移动基片上的薄膜来控制薄膜形成过程。与移动基板相关联的配准特征可以与信号系统结合使用，以确定移动基板的位置，由此可以执行移动基板上对应位置的可重复分析。散射测量允许原位测量薄膜形成进程，由此可以在反馈回路中控制薄膜形成工艺条件以获得目标结果。也可以通过在基板的非生产部分上提供光栅图案来促进散射测量。

20. 发明授权

US06552790B1 System and method for facilitating wafer alignment by mitigating effects of reticle rotation on overlay 有权
标题翻译：用于通过减轻掩模旋转对覆盖层的影响来促进晶片对准的系统和方法
公开(公告)号：US06552790B1
公开(公告)日：2003-04-22
申请号：US09788905
申请日：2001-02-20
申请人： Michael K. Templeton , Bharath Rangarajan
发明人： Michael K. Templeton , Bharath Rangarajan
IPC分类号： G01B1100
CPC分类号： G03F7/70633 , G03F9/7003 , G03F9/7076 , G03F9/7084
摘要： The present invention relates to wafer alignment. A reticle is employed which includes, a design, and a first and second set of scribe marks. The first and second sets of scribe marks have an associated symmetry relative to the reticle design. The design and scribe marks are printed at selected field locations on a surface layer of the wafer. The first and second sets of scribe marks as printed at adjacent fields on the surface layer of wafer form a composite set of scribe marks. The symmetric relationship between the first and second sets of scribe marks results in the composite set of scribe marks substantially negating print errors of the marks due to reticle rotation and/or lens magnification with respect to a geometric reference point of the composite set of scribe marks. The employment of the composite set of scribe marks, such as to locate a corresponding virtual alignment mark, substantially facilitates mitigation of overlay error in wafer alignment.
摘要翻译：本发明涉及晶圆对准。使用掩模版，其包括设计，以及第一和第二组划线标记。第一组和第二组划痕具有相对于标线设计的相关对称性。设计和划痕被印在晶片的表面层上的选定的场地。在晶片表面层上的相邻场印刷的第一组和第二组刻痕形成一组复合的划线标记。第一组和第二组划线标记之间的对称关系导致划线标记的复合组合基本上抵消了由于标线转动和/或透镜倍率而导致的标记的印刷误差相对于复合组划线标记的几何参考点。使用复合组划线标记，例如定位相应的虚拟对准标记，基本上有助于减轻晶片对准中的重叠误差。

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