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11. 发明申请

US20060223290A1 METHOD OF PRODUCING HIGHLY STRAINED PECVD SILICON NITRIDE THIN FILMS AT LOW TEMPERATURE 失效
标题翻译：在低温下生产高应变PECVD硅氮化物薄膜的方法
公开(公告)号：US20060223290A1
公开(公告)日：2006-10-05
申请号：US10907454
申请日：2005-04-01
申请人： Michael Belyansky , Oleg Gluschenkov , Ying Li , Anupama Mallikarjunan
发明人： Michael Belyansky , Oleg Gluschenkov , Ying Li , Anupama Mallikarjunan
IPC分类号： H01L21/265 , H01L21/31
CPC分类号： H01L21/0217 , C23C16/345 , C23C16/45523 , H01L21/02271 , H01L21/02274 , H01L21/3185 , H01L21/823807 , H01L21/823864 , H01L29/7833 , H01L29/7843
摘要： A method for increasing the level of stress for amorphous thin film stressors by means of modifying the internal structure of such stressors is provided. The method includes first forming a first portion of an amorphous film stressor material on at least a surface of a substrate, said first portion having a first state of mechanical strain defining a first stress value. After the forming step, the first portion of the amorphous film stressor material is densified such that the first state of mechanical strain is not substantially altered, while increasing the first stress value. In some embodiments, the steps of forming and densifying are repeated any number of times to obtain a preselected and desired thickness for the stressor.
摘要翻译：提供了通过改变这种压力源的内部结构来增加非晶薄膜应力的应力水平的方法。该方法包括首先在基底的至少一个表面上形成非晶膜应力材料的第一部分，所述第一部分具有限定第一应力值的第一机械应变状态。在成形步骤之后，非晶态应力材料的第一部分被致密化，使得在增加第一应力值的同时，基本上不改变机械应变的第一状态。在一些实施例中，形成和致密化的步骤重复任意次数，以获得应激源的预选和期望的厚度。

12. 发明申请

US20050093059A1 Structure and method to improve channel mobility by gate electrode stress modification 有权
标题翻译：通过栅电极应力改变来提高沟道迁移率的结构和方法
公开(公告)号：US20050093059A1
公开(公告)日：2005-05-05
申请号：US10695752
申请日：2003-10-30
申请人： Michael Belyansky , Dureseti Chidambarrao , Omer Dokumaci , Bruce Deris , Oleg Gluschenkov
发明人： Michael Belyansky , Dureseti Chidambarrao , Omer Dokumaci , Bruce Deris , Oleg Gluschenkov
IPC分类号： H01L21/20 , H01L21/28 , H01L21/302 , H01L21/336 , H01L21/44 , H01L21/461 , H01L21/4763 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/72 , H01L29/78 , H01L29/786 , H01L31/062
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4908 , H01L29/66795 , H01L29/785
摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and PFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi2, NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.
摘要翻译：在制造包括nFET和PFET的互补金属氧化物半导体（CMOS）场效应晶体管的情况下，通过使栅电极的材料与金属反应来增强或调节载流子迁移率，以产生应力合金（优选CoSi 2Si，NiSi或PdSi）。在nFET和pFET两者的情况下，各合金的固有应力对相应晶体管的沟道产生相反的应力。通过在nFET和pFET合金或硅化物中保持相反的应力，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。

13. 发明申请

US20080020522A1 FIELD EFFECT TRANSISTORS WITH DIELECTRIC SOURCE DRAIN HALO REGIONS AND REDUCED MILLER CAPACITANCE 有权
标题翻译：具有介质源漏极区域的场效应晶体管和减少的MILLER电容
公开(公告)号：US20080020522A1
公开(公告)日：2008-01-24
申请号：US11865313
申请日：2007-10-01
申请人： Michael Belyansky , Dureseti Chidambarrao , Oleg Gluschenkov
发明人： Michael Belyansky , Dureseti Chidambarrao , Oleg Gluschenkov
IPC分类号： H01L21/336
CPC分类号： H01L29/0653 , H01L29/1083 , H01L29/6653 , H01L29/66636 , H01L29/66772 , H01L29/7833 , H01L29/7842 , H01L29/7843 , H01L29/78609 , Y10S438/954
摘要： A field effect transistor (FET) device includes a gate conductor and gate dielectric formed over an active device area of a semiconductor substrate. A drain region is formed in the active device area of the semiconductor substrate, on one side of the gate conductor, and a source region is formed in the active device area of the semiconductor substrate, on an opposite side of the gate conductor. A dielectric halo or plug is formed in the active area of said semiconductor substrate, the dielectric halo or plug disposed in contact between the drain region and a body region, and in contact between the source region and the body region.
摘要翻译：场效应晶体管（FET）器件包括在半导体衬底的有源器件区域上形成的栅极导体和栅极电介质。在半导体衬底的有源器件区域中，在栅极导体的一侧上形成漏极区域，并且在栅极导体的相对侧上在半导体衬底的有源器件区域中形成源极区域。在所述半导体衬底的有源区域中形成介电晕或插塞，所述介电晕或插头设置在所述漏区和体区之间并且在所述源区与所述体区之间接触。

14. 发明授权

US06890833B2 Trench isolation employing a doped oxide trench fill 失效
标题翻译：使用掺杂氧化物沟槽填充的沟槽隔离
公开(公告)号：US06890833B2
公开(公告)日：2005-05-10
申请号：US10397761
申请日：2003-03-26
申请人： Michael Belyansky , Andreas Knorr , Oleg Gluschenkov , Christopher Parks
发明人： Michael Belyansky , Andreas Knorr , Oleg Gluschenkov , Christopher Parks
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A trench isolation structure is formed in a substrate. One or more openings are formed in a surface of the substrate, and a liner layer is deposited at least along a bottom and sidewalls of the openings. A layer of doped oxide material is deposited at least in the openings, and the substrate is annealed to reflow the layer of doped oxide material. Only a portion near the surface of the substrate is removed from the layer of doped oxide material in the opening. A cap layer is deposited atop a remaining portion of the layer of doped oxide material in the opening.
摘要翻译：在衬底中形成沟槽隔离结构。在基板的表面中形成一个或多个开口，并且至少沿着开口的底部和侧壁沉积衬垫层。至少在开口中沉积一层掺杂的氧化物材料，并且将衬底退火以回流掺杂的氧化物材料层。仅在基片表面附近的部分从开口中的掺杂氧化物材料层中除去。覆盖层沉积在开口中掺杂氧化物材料层的剩余部分的顶部。

15. 发明申请

US20070063278A1 HIGHLY MANUFACTURABLE SRAM CELLS IN SUBSTRATES WITH HYBRID CRYSTAL ORIENTATION 有权
标题翻译：具有混合晶体取向的衬底中的高度可制造的SRAM电池
公开(公告)号：US20070063278A1
公开(公告)日：2007-03-22
申请号：US11162780
申请日：2005-09-22
申请人： Bruce Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
发明人： Bruce Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
IPC分类号： H01L27/12
CPC分类号： H01L27/1104 , H01L27/11 , Y10S257/903 , Y10S438/973
摘要： The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.
摘要翻译：本发明涉及一种半导体器件结构，其包括在衬底中形成的至少一个SRAM单元。这样的SRAM单元包括两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。下拉晶体管和栅极晶体管在沟道宽度上基本相似，并且具有基本相似的源极 - 漏极掺杂浓度，而SRAM单元的β比率至少为1.5。衬底优选地包括具有两个分离的区域集合的混合衬底，而这两组区域中的载流子迁移率以至少约1.5的因子差分。更优选地，SRAM单元的下拉晶体管形成在一组区域中，并且栅极晶体管形成在另一组区域中，使得下拉晶体管中的电流大于传输栅晶体管。

16. 发明申请

US20050158924A1 Polycrystalline Silicon Layer With Nano-grain Structure and Method of Manufacture 失效
标题翻译：具有纳米晶粒结构的多晶硅层和制造方法
公开(公告)号：US20050158924A1
公开(公告)日：2005-07-21
申请号：US10707878
申请日：2004-01-20
申请人： Ashima Chakravarti , Bruce Doris , Romany Ghali , Oleg Gluschenkov , Michael Gribelyuk , Woo-Hyeong Lee , Anita Madan
发明人： Ashima Chakravarti , Bruce Doris , Romany Ghali , Oleg Gluschenkov , Michael Gribelyuk , Woo-Hyeong Lee , Anita Madan
IPC分类号： C23C16/24 , C23C16/46 , H01L21/00 , H01L21/205 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： C23C16/24 , C23C16/46 , H01L21/28035 , H01L21/32055 , H01L29/4925
摘要： A method of forming polycrystalline silicon with ultra-small grain sizes employs a differential heating of the upper and lower sides of the substrate of a CVD apparatus, in which the lower side of the substrate receives considerably more power than the upper side, preferable more than 75% of the power; and in which the substrate is maintained during deposition at a temperature more than 50° C. above the 550° C. crystallization temperature of silicon.
摘要翻译：形成超小晶粒尺寸的多晶硅的方法采用CVD装置的衬底的上侧和下侧的差分加热，其中衬底的下侧比上侧受到明显更多的功率，优选大于 75％的权力; 并且其中在超过550℃的硅结晶温度超过50℃的温度下在沉积期间保持基底。

17. 发明申请

US20080090366A1 Hybrid SOI-Bulk Semiconductor Transistors 失效
标题翻译：混合SOI-体半导体晶体管
公开(公告)号：US20080090366A1
公开(公告)日：2008-04-17
申请号：US11870436
申请日：2007-10-11
申请人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
发明人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/7849 , H01L29/0653 , H01L29/1054 , H01L29/7842 , H01L29/78603 , H01L29/78612 , H01L29/78618 , H01L29/78687
摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
摘要翻译：场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。携带者的流动性可能会与其他有利的影响相结合。

18. 发明申请

US20060125008A1 DUAL STRESSED SOI SUBSTRATES 有权
标题翻译：双应力SOI衬底
公开(公告)号：US20060125008A1
公开(公告)日：2006-06-15
申请号：US10905062
申请日：2004-12-14
申请人： Dureseti Chidambarrao , Bruce Doris , Oleg Gluschenkov , Omer Dokumaci , Huilong Zhu
发明人： Dureseti Chidambarrao , Bruce Doris , Oleg Gluschenkov , Omer Dokumaci , Huilong Zhu
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7843 , Y10S438/938
摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.
摘要翻译：本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层; 以及在所述衬底顶部的第二层叠堆叠，所述第二层叠堆叠包括位于所述衬底顶部的拉伸介电层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

19. 发明申请

US20060060925A1 SEMICONDUCTOR DEVICE STRUCTURE WITH ACTIVE REGIONS HAVING DIFFERENT SURFACE DIRECTIONS AND METHODS 有权
标题翻译：具有不同表面方向的活动区域的半导体器件结构和方法
公开(公告)号：US20060060925A1
公开(公告)日：2006-03-23
申请号：US10711416
申请日：2004-09-17
申请人： Bruce Doris , Oleg Gluschenkov , MeiKei Ieong , Effendi Leobandung , Huilong Zhu
发明人： Bruce Doris , Oleg Gluschenkov , MeiKei Ieong , Effendi Leobandung , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L29/045 , H01L21/76275 , H01L21/76278 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/7842
摘要： Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and a first surface orientation atop a second wafer having a different second surface orientation and a different second surface direction; forming an opening through the first wafer to the second wafer; and forming a region in the opening coplanar with a surface of the first wafer, wherein the region has the second surface orientation and the second surface direction. The semiconductor device structure includes at least two active regions having different surface directions, each active region including one of a plurality of nFETs and a plurality of pFETs, and wherein a gate electrode orientation is such that the nFETs and the pFETs are substantially parallel to each other.
摘要翻译：公开了同时实现nFET和pFET器件以及朝向一个方向的栅极的最佳应力类型和电流流动的半导体结构和方法。该方法的一个实施例包括将具有第一表面方向的第一晶片和具有不同的第二表面取向和不同的第二表面方向的第二晶片顶部的第一表面取向接合; 形成通过所述第一晶片的开口到所述第二晶片; 以及在所述开口中形成与所述第一晶片的表面共面的区域，其中所述区域具有第二表面取向和所述第二表面方向。半导体器件结构包括具有不同表面方向的至少两个有源区，每个有源区包括多个nFET和多个pFET中的一个，并且其中栅电极取向使得nFET和pFET基本上平行于每个其他。

20. 发明申请

US20060043421A1 MULTI-GATE DEVICE WITH HIGH K DIELECTRIC FOR CHANNEL TOP SURFACE 有权
标题翻译：具有高K介质的通道顶表面的多栅极器件
公开(公告)号：US20060043421A1
公开(公告)日：2006-03-02
申请号：US10711200
申请日：2004-09-01
申请人： Bruce Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
发明人： Bruce Doris , Oleg Gluschenkov , Ying Zhang , Huilong Zhu
IPC分类号： H01L27/10
CPC分类号： H01L29/785 , H01L29/66795
摘要： A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the channel. The use of the high-k dielectric layer on the top surface reduces hysteresis and mobility degradation associated with high-k dielectrics. The protection layer may protect the high-k dielectric layer during an etching process.
摘要翻译：多栅极器件具有用于栅极顶部沟道的高k电介质层和用于finFET器件的保护层。高k电介质层被放置在finFET的沟道的顶表面上，并且可以减少或消除沟道中的硅消耗。在顶表面上使用高k电介质层减少了与高k电介质相关的滞后和迁移率降低。保护层可以在蚀刻过程中保护高k电介质层。

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