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11. 发明授权

US06831653B2 Graphics pixel packing for improved fill rate performance 有权
标题翻译：图形像素包装，提高填充率性能
公开(公告)号：US06831653B2
公开(公告)日：2004-12-14
申请号：US09919551
申请日：2001-07-31
申请人： David Kehlet , Nandini Ramani , Yan Yan Tang , Roger W. Swanson
发明人： David Kehlet , Nandini Ramani , Yan Yan Tang , Roger W. Swanson
IPC分类号： G09G536
CPC分类号： G06T1/60
摘要： A system and method for packing pixels together to provide a increased fill rate in a frame buffer hardware in the graphics system. The graphics system may be configured to receive and rasterize graphics data at a faster cycle rate than the system's frame buffer memory fill rate. The output from the rasterization hardware may be stored in a FIFO memory that is configured to selectively shift pixels in order to improve fill rate performance. The FIFO memory may be configured to ensure that the pixels meet certain criteria in order to prevent page faults and interleave conflicts that could reduce the fill rate. The FIFO memory may also be configured to remove empty cycles that occur as a result of the pixel packing.
摘要翻译：一种用于将像素打包在一起以在图形系统中的帧缓冲器硬件中提供增加的填充率的系统和方法。图形系统可以被配置为以比系统的帧缓冲存储器填充速率更快的周期速率接收和光栅化图形数据。光栅化硬件的输出可以存储在FIFO存储器中，FIFO存储器被配置为选择性地移位像素以便提高填充率性能。 FIFO存储器可以被配置为确保像素满足特定标准，以便防止可能降低填充率的页错误和交错冲突。 FIFO存储器还可以被配置为去除由于像素打包而发生的空循环。

12. 发明授权

US08321761B1 ECC bits used as additional register file storage 有权
公开(公告)号：US08321761B1
公开(公告)日：2012-11-27
申请号：US12568552
申请日：2009-09-28
申请人： Fred Gruner , Xiaogang Qiu , Yan Yan Tang
发明人： Fred Gruner , Xiaogang Qiu , Yan Yan Tang
IPC分类号： G11C29/00
CPC分类号： G09G5/363 , G06F11/10 , G09G2330/12 , G09G2360/121 , G09G2360/125 , G11C2029/0411
摘要： A memory module includes a plurality of register files. Each register file is associated with a set of error-correcting code (ECC) bits and ECC check/correct logic that can provide error-correcting functionality, if required. When error-correcting functionality is not required, ECC bits are grouped together to form additional register files, thereby providing additional storage space.

13. 发明授权

US06927775B2 Parallel box filtering through reuse of existing circular filter 有权
标题翻译：通过重复使用现有的圆形滤波器并行框过滤
公开(公告)号：US06927775B2
公开(公告)日：2005-08-09
申请号：US10377924
申请日：2003-03-03
申请人： Michael W. Schimpf , Yan Yan Tang
发明人： Michael W. Schimpf , Yan Yan Tang
IPC分类号： G06T15/00 , G06T15/50 , G06F15/16
CPC分类号： G06T15/503 , G06T15/005
摘要： A sample filtering system and method for concurrently filtering sample data for two or more sequential pixels (in a scan-line) are disclosed. The system may include a sample cache, a control register, a read cache controller, and a sample-to-pixel calculation unit. The read cache controller reads a first set of S samples from the sample cache, and outputs a second set of S samples to the sample-to-pixel calculation unit. The second set of samples may have one or more subsets of samples, with each subset of samples selected to cover the filter region for one of the sequential pixels. The sample-to-pixel calculation unit may process each subset separately and concurrently.
摘要翻译：公开了用于同时过滤两个或更多个顺序像素（扫描线）的采样数据的采样滤波系统和方法。系统可以包括采样高速缓存，控制寄存器，读高速缓存控制器和采样到像素计算单元。读取高速缓存控制器从采样高速缓存读取第一组S采样，并将第二组S采样输出到采样到像素的计算单元。第二组样本可以具有一个或多个样本子集，其中每个样本子集被选择以覆盖顺序像素之一的滤波器区域。样本到像素计算单元可以分别地并发地处理每个子集。

14. 发明授权

US06914609B2 Multiple scan line sample filtering 有权
标题翻译：多扫描线样本滤波
公开(公告)号：US06914609B2
公开(公告)日：2005-07-05
申请号：US10085636
申请日：2002-02-28
申请人： Yan Yan Tang , Wayne Eric Burk , Philip C. Leung
发明人： Yan Yan Tang , Wayne Eric Burk , Philip C. Leung
IPC分类号： G09G5/36
CPC分类号： G09G5/363
摘要： A system and method for generating pixels for a display device. The system may include a sample buffer for storing a plurality samples in a memory, a sample cache for caching recently accessed samples, and a sample filter unit for filtering one or more samples to generate a pixel. The generated pixels may then be stored in a frame buffer or provided to a display device. The method operates to take advantage of the common samples shared by neighboring pixels in both the x and y directions for reduced sample buffer accesses and improved performance. The method involves reading samples from the memory that correspond to pixels in a plurality of neighboring scan lines, and possibly also to multiple pixels in each of these scan lines. The samples may be stored in a cache memory and then accessed from the cache memory for filtering. The method maximizes use of the common samples shared by neighboring pixels in both the x and y directions.
摘要翻译：一种用于生成显示装置的像素的系统和方法。系统可以包括用于将多个样本存储在存储器中的样本缓冲器，用于缓存最近访问的样本的样本缓存器，以及用于对一个或多个样本进行过滤以生成像素的样本滤波器单元。所产生的像素然后可以存储在帧缓冲器中或提供给显示设备。该方法操作以利用x和y方向上的相邻像素共享的公共样本，以减少采样缓冲器访问和改进的性能。该方法涉及从存储器中读取与多个相邻扫描线中的像素相对应的样本，并且还可能读取这些扫描线中的每一个中的多个像素。样本可以存储在高速缓冲存储器中，然后从高速缓存存储器进行过滤。该方法最大限度地利用x和y方向上相邻像素共享的公共样本。

15. 发明授权

US08533435B2 Reordering operands assigned to each one of read request ports concurrently accessing multibank register file to avoid bank conflict 有权
标题翻译：对分配给每个读取请求端口的操作数重新排序并发访问多银行寄存器文件以避免银行冲突
公开(公告)号：US08533435B2
公开(公告)日：2013-09-10
申请号：US12875843
申请日：2010-09-03
申请人： Xiaogang Qiu , Ming Y. Siu , Yan Yan Tang , John Erik Lindholm , Michael C. Shebanow , Stuart F. Oberman
发明人： Xiaogang Qiu , Ming Y. Siu , Yan Yan Tang , John Erik Lindholm , Michael C. Shebanow , Stuart F. Oberman
IPC分类号： G06F9/34
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles.
摘要翻译：本发明的一个实施例提出了一种用于收集由指令指定的操作数的技术。由于接收到指令序列，指令指定的操作数被分配给端口，以便将由单个指令指定的每个操作数分配给不同的端口。通过从不同端口中的每一个选择一个操作数来调度来自多存储器寄存器文件的操作数，以产生操作数读取请求，并确保所选择的操作数中的两个或更多个不存储在多个存储区的同一个存储区中银行寄存器文件。由操作数读取请求指定的操作数在单个时钟周期内从多存储体寄存器文件读取。然后由指令指定的操作数从多存储寄存器文件中读取并在一个或多个时钟周期内采集，执行每条指令。

16. 发明授权

US07999817B1 Buffering unit to support graphics processing operations 有权
标题翻译：缓冲单元支持图形处理操作
公开(公告)号：US07999817B1
公开(公告)日：2011-08-16
申请号：US11556051
申请日：2006-11-02
申请人： Andrew J. Tao , Vimal S. Parikh , Yan Yan Tang
发明人： Andrew J. Tao , Vimal S. Parikh , Yan Yan Tang
IPC分类号： G06T1/60
CPC分类号： G06T1/00
摘要： An apparatus and method for buffering graphics data are described. In one embodiment, a graphics processing apparatus includes a memory and a buffering unit that is connected to the memory. The buffering unit is configured to buffer vertex attributes en route to the memory. The buffering unit is configured to coalesce a subset of the vertex attributes to be stored within a common range of addresses in the memory, and the buffering unit is configured to issue a single write request to the memory on behalf of the subset of the vertex attributes.
摘要翻译：描述用于缓冲图形数据的装置和方法。在一个实施例中，图形处理装置包括存储器和连接到存储器的缓冲单元。缓冲单元被配置为缓冲到存储器的途中的顶点属性。缓冲单元被配置为将要存储在存储器中的公共地址范围内的顶点属性的子集合并且缓冲单元被配置为代表顶点属性的子集向存储器发出单个写入请求。

17. 发明申请

US20110072243A1 Unified Collector Structure for Multi-Bank Register File 有权
标题翻译：多银行登记册统一采集器结构
公开(公告)号：US20110072243A1
公开(公告)日：2011-03-24
申请号：US12875843
申请日：2010-09-03
申请人： Xiaogang Qiu , Ming Y. Siu , Yan Yan Tang , John Erik Lindholm , Michael C. Shebanow , Stuart F. Oberman
发明人： Xiaogang Qiu , Ming Y. Siu , Yan Yan Tang , John Erik Lindholm , Michael C. Shebanow , Stuart F. Oberman
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/3824 , G06F9/3851 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles.
摘要翻译：本发明的一个实施例提出了一种用于收集由指令指定的操作数的技术。由于接收到指令序列，指令指定的操作数被分配给端口，以便将由单个指令指定的每个操作数分配给不同的端口。通过从不同端口中的每一个选择一个操作数来调度来自多存储器寄存器文件的操作数，以产生操作数读取请求，并确保所选择的操作数中的两个或更多个不存储在多个存储区的同一个存储区中银行寄存器文件。由操作数读取请求指定的操作数在单个时钟周期内从多存储体寄存器文件读取。然后由指令指定的操作数从多存储寄存器文件中读取并在一个或多个时钟周期内采集，执行每条指令。

18. 发明申请

US20110069076A1 REGISTER INDEXED SAMPLER FOR TEXTURE OPCODES 有权
标题翻译：用于纹理操作码的注册表索引器
公开(公告)号：US20110069076A1
公开(公告)日：2011-03-24
申请号：US12868586
申请日：2010-08-25
申请人： John Erik LINDHOLM , Yan Yan Tang
发明人： John Erik LINDHOLM , Yan Yan Tang
IPC分类号： G06T11/40
CPC分类号： G06T11/001 , G06T11/40
摘要： One embodiment of the present invention sets forth a technique for dynamically specifying a texture header and texture sampler using an index. The index corresponds to a particular register value that may be static or computed during execution of a shader program. Any texture operation instruction may specify an index value for each of the texture header and the texture sampler.
摘要翻译：本发明的一个实施例提出了一种使用索引动态地指定纹理头和纹理采样器的技术。索引对应于在执行着色器程序期间可以是静态的或计算的特定寄存器值。任何纹理操作指令都可以为每个纹理头和纹理采样器指定一个索引值。

19. 发明授权

US08700877B2 Address mapping for a parallel thread processor 有权
标题翻译：并行线程处理器的地址映射
公开(公告)号：US08700877B2
公开(公告)日：2014-04-15
申请号：US12890518
申请日：2010-09-24
申请人： Michael C. Shebanow , Yan Yan Tang , John R. Nickolls
发明人： Michael C. Shebanow , Yan Yan Tang , John R. Nickolls
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0284 , G06F9/3851 , G06F12/0607
摘要： A method for thread address mapping in a parallel thread processor. The method includes receiving a thread address associated with a first thread in a thread group; computing an effective address based on a location of the thread address within a local window of a thread address space; computing a thread group address in an address space associated with the thread group based on the effective address and a thread identifier associated with a first thread; and computing a virtual address associated with the first thread based on the thread group address and a thread group identifier, where the virtual address is used to access a location in a memory associated with the thread address to load or store data.
摘要翻译：一种并行线程处理器中线程地址映射的方法。该方法包括接收与线程组中的第一线程相关联的线程地址; 基于线程地址在线程地址空间的本地窗口内的位置来计算有效地址; 基于有效地址和与第一线程相关联的线程标识符计算与线程组相关联的地址空间中的线程组地址; 以及基于所述线程组地址和线程组标识符计算与所述第一线程相关联的虚拟地址，其中所述虚拟地址用于访问与所述线程地址相关联的存储器中的位置以加载或存储数据。

20. 发明授权

US08266382B1 Cache interface protocol including arbitration and hints 有权
标题翻译：缓存接口协议包括仲裁和提示
公开(公告)号：US08266382B1
公开(公告)日：2012-09-11
申请号：US12650214
申请日：2009-12-30
申请人： Alexander L. Minkin , Steven J. Heinrich , Rajeshwaran Selvanesan , Charles McCarver , Stewart Glenn Carlton , Anjana Rajendran , Yan Yan Tang
发明人： Alexander L. Minkin , Steven J. Heinrich , Rajeshwaran Selvanesan , Charles McCarver , Stewart Glenn Carlton , Anjana Rajendran , Yan Yan Tang
IPC分类号： G06F13/00 , G06F13/28 , G06F3/00 , G06F5/00
CPC分类号： G06F13/28
摘要： One embodiment of the present invention sets forth a technique for arbitrating requests received from one of the multiple clients of an L1 cache and for providing hints to the client to assist in arbitration. The L1 cache services multiple clients with diverse latency and bandwidth requirements and may be reconfigured to provide memory spaces for clients executing multiple parallel threads, where the memory spaces each have a different scope.
摘要翻译：本发明的一个实施例提出了一种用于仲裁从L1高速缓存的多个客户机中的一个接收的请求并且向客户端提供帮助以协助仲裁的技术。 L1缓存服务于具有不同延迟和带宽需求的多个客户端，并且可以被重新配置为为执行多个并行线程的客户端提供存储空间，其中每个存储空间具有不同的范围。

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