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11. 发明授权

US08274157B2 Semiconductor device and a method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08274157B2
公开(公告)日：2012-09-25
申请号：US12883278
申请日：2010-09-16
申请人： Yuki Koide , Masataka Minami
发明人： Yuki Koide , Masataka Minami
IPC分类号： H01L23/48
CPC分类号： H01L24/12 , H01L23/3114 , H01L23/522 , H01L23/525 , H01L24/05 , H01L2224/0231 , H01L2224/0401 , H01L2224/0558 , H01L2224/05644 , H01L2224/13099 , H01L2224/13111 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/1306 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second patterns are coexistent within the plane of the semiconductor substrate, and the occupation ratio of the total of the first patterns and the second patterns within the plane of the semiconductor substrate, that is, the occupation ratio of the redistribution interconnects is 35 to 60%.
摘要翻译：一种半导体器件，其具有WPP技术中的再分配互连和改善的可靠性，其中再分配互连具有在半导体衬底的平面内彼此电分离的第一图案和第二图案，第一图案电耦合到多层互连并且浮置的第二图案在半导体衬底的平面内共存，并且半导体衬底的平面内的第一图案和第二图案的总和占据比例，即再分布互连的占有率为35 至60％。

12. 发明授权

US08127368B2 Semiconductor memory card and data reading apparatus, and data reading/reproducing apparatus 有权
标题翻译：半导体存储卡和数据读取装置以及数据读取/重放装置
公开(公告)号：US08127368B2
公开(公告)日：2012-02-28
申请号：US11979035
申请日：2007-10-30
申请人： Teruto Hirota , Makoto Tatebayashi , Taihei Yugawa , Masataka Minami , Masayuki Kozuka
发明人： Teruto Hirota , Makoto Tatebayashi , Taihei Yugawa , Masataka Minami , Masayuki Kozuka
IPC分类号： G06F21/00
CPC分类号： G06F21/10 , G06F21/445 , G06F21/6218 , G06F21/78 , G06F21/79 , G06F2221/2105 , G06Q20/3674 , G11C16/22 , H04L9/3273 , H04L2209/603
摘要： A semiconductor memory card comprising a control IC 302, a flash memory 303, and a ROM 304. The ROM 304 holds information such as a medium ID 341 unique to the semiconductor memory card. The flash memory 303 includes an authentication memory 332 and a non-authentication memory 331. The authentication memory 332 can be accessed only by external devices which have been affirmatively authenticated. The non-authentication memory 331 can be accessed by external devices whether the external devices have been affirmatively authenticated or not. The control IC 302 includes control units 325 and 326, an authentication unit 321 and the like. The control units 325 and 326 control accesses to the authentication memory 332 and the non-authentication memory 331, respectively. The authentication unit 321 executes a mutual authentication with an external device.
摘要翻译：包括控制IC302，闪速存储器303和ROM304的半导体存储卡.ROM 304保存诸如半导体存储卡唯一的介质ID 341之类的信息。闪速存储器303包括认证存储器332和非验证存储器331.认证存储器332可以仅被已被肯定认证的外部设备访问。外部设备可以访问非认证存储器331，无论外部设备是否被肯定认证。控制IC302包括控制单元325和326，认证单元321等。控制单元325和326分别控制对认证存储器332和非验证存储器331的访问。认证单元321执行与外部设备的相互认证。

13. 发明申请

US20110001236A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110001236A1
公开(公告)日：2011-01-06
申请号：US12883278
申请日：2010-09-16
申请人： YUKI KOIDE , Masataka Minami
发明人： YUKI KOIDE , Masataka Minami
IPC分类号： H01L23/48
CPC分类号： H01L24/12 , H01L23/3114 , H01L23/522 , H01L23/525 , H01L24/05 , H01L2224/0231 , H01L2224/0401 , H01L2224/0558 , H01L2224/05644 , H01L2224/13099 , H01L2224/13111 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/1306 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second patterns are coexistent within the plane of the semiconductor substrate, and the occupation ratio of the total of the first patterns and the second patterns within the plane of the semiconductor substrate, that is, the occupation ratio of the redistribution interconnects is 35 to 60%.
摘要翻译：一种半导体器件，其具有WPP技术中的再分配互连和改善的可靠性，其中再分配互连具有在半导体衬底的平面内彼此电分离的第一图案和第二图案，第一图案电耦合到多层互连并且浮置的第二图案在半导体衬底的平面内共存，并且半导体衬底的平面内的第一图案和第二图案的总和占据比例，即再分布互连的占有率为35 至60％。

14. 发明申请

US20060129819A1 Semiconductor memory card and data reading apparatus, and data reading/reproducing apparatus 有权
标题翻译：半导体存储卡和数据读取装置以及数据读取/重放装置
公开(公告)号：US20060129819A1
公开(公告)日：2006-06-15
申请号：US11350092
申请日：2006-02-09
申请人： Teruto Hirota , Makoto Tatebayashi , Taihei Yugawa , Masataka Minami , Masayuki Kozuka
发明人： Teruto Hirota , Makoto Tatebayashi , Taihei Yugawa , Masataka Minami , Masayuki Kozuka
IPC分类号： H04L9/00
CPC分类号： G06F21/10 , G06F21/445 , G06F21/6218 , G06F21/78 , G06F21/79 , G06F2221/2105 , G06Q20/3674 , G11C16/22 , H04L9/3273 , H04L2209/603
摘要： A semiconductor memory card comprising a control IC 302, a flash memory 303, and a ROM 304. The ROM 304 holds information such as a medium ID 341 unique to the semiconductor memory card. The flash memory 303 includes an authentication memory 332 and a non-authentication memory 331. The authentication memory 332 can be accessed only by external devices which have been affirmatively authenticated. The non-authentication memory 331 can be accessed by external devices whether the external devices have been affirmatively authenticated or not. The control IC 302 includes control units 325 and 326, an authentication unit 321 and the like. The control units 325 and 326 control accesses to the authentication memory 332 and the non-authentication memory 331, respectively. The authentication unit 321 executes a mutual authentication with an external device.
摘要翻译：包括控制IC302，闪速存储器303和ROM304的半导体存储卡.ROM 304保存诸如半导体存储卡唯一的介质ID 341之类的信息。闪速存储器303包括认证存储器332和非验证存储器331.认证存储器332可以仅被已被肯定认证的外部设备访问。外部设备可以访问非认证存储器331，无论外部设备是否被肯定认证。控制IC302包括控制单元325和326，认证单元321等。控制单元325和326分别控制对认证存储器332和非验证存储器331的访问。认证单元321执行与外部设备的相互认证。

15. 发明申请

US20050146961A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20050146961A1
公开(公告)日：2005-07-07
申请号：US11042172
申请日：2005-01-26
申请人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
发明人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC分类号： H01L27/10 , H01L21/8244 , H01L27/11 , G11C7/02
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.
摘要翻译：现有的已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底进行电接触，这将导致不对称性导致了微图案化困难的问题的发生。为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分为两部分，它们设置在N型阱区NW 1的相对侧，并形成为形成晶体管的扩散层没有曲率，同时使得布局方向在平行于边界线和位线的方向上运行。在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。

16. 发明授权

US06906551B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06906551B2
公开(公告)日：2005-06-14
申请号：US10154956
申请日：2002-05-28
申请人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
发明人： Hiroyuki Mizuno , Masataka Minami , Koichiro Ishibashi , Masayuki Miyazaki
IPC分类号： H01L27/092 , H01L27/105 , H03K3/01
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor integrated circuit device comprising a logical circuit including a MIS transistor formed on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor forming the logical circuit, an oscillation circuit including a MIS transistor formed on the semiconductor substrate, the oscillation circuit being constructed so that the frequency of an oscillation output thereof can be made variable, and a buffer circuit, in which the control circuit is supplied with a clock signal having a predetermined frequency and the oscillation output of the oscillation circuit so that the control circuit compares the frequency of the oscillation output and the frequency of the clock signal to output a first control signal, the oscillation circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal, the control of the frequency of the oscillation output being performed in such a manner that the first control signal controls a threshold voltage of the MIS transistor forming the oscillation circuit, and the buffer circuit is constructed so that it is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor forming the logical circuit.
摘要翻译：一种半导体集成电路器件，包括一个逻辑电路，该逻辑电路包括形成在半导体衬底上的MIS晶体管，用于控制形成逻辑电路的MIS晶体管的阈值电压的控制电路，包括形成在半导体衬底上的MIS晶体管的振荡电路，振荡电路被构造成使得其振荡输出的频率可以变化;以及缓冲电路，其中向控制电路提供具有预定频率的时钟信号和振荡电路的振荡输出，使得控制电路将振荡输出的频率和时钟信号的频率进行比较以输出第一控制信号，振荡电路由第一控制信号控制，使得振荡输出的频率对应于时钟信号的频率，控制振荡输出的频率 d，使得第一控制信号控制形成振荡电路的MIS晶体管的阈值电压，并且缓冲电路被构造成输入第一控制信号以输出与第一控制相对应的第二控制信号信号，所述第二控制信号控制构成所述逻辑电路的所述MIS晶体管的阈值电压。

17. 发明授权

US06862582B2 Production protection system dealing with contents that are digital production 有权
标题翻译：处理数字化生产的内容的生产保护体系
公开(公告)号：US06862582B2
公开(公告)日：2005-03-01
申请号：US10729186
申请日：2003-12-05
申请人： Shunji Harada , Masayuki Kozuka , Masataka Minami , Makoto Tatebayashi
发明人： Shunji Harada , Masayuki Kozuka , Masataka Minami , Makoto Tatebayashi
IPC分类号： G09C1/00 , G06F1/00 , G06F1/16 , G06F21/10 , G06F17/60
CPC分类号： G06F21/10 , G06F2211/007 , G06F2221/2107
摘要： A data protection system obtains data having a first content on which a first encryption has been performed and a second content on which a second encryption has been performed, the second encryption more difficult to break than the first encryption. A first content decryption unit decrypts the first content, using a first encryption method corresponding to the first encryption of the first content. A second content decryption unit decrypts the second content using a second decryption method that corresponds to the second encryption. The decrypting contents can be executed by a software, and the second content decryption unit can include one of tamperproof hardware and an apparatus that executes tamperproof software.
摘要翻译：数据保护系统获得具有已经执行了第一加密的第一内容和已经执行了第二加密的第二内容的数据，第二加密比第一加密更难打破。第一内容解密单元使用与第一内容的第一加密相对应的第一加密方法来解密第一内容。第二内容解密单元使用对应于第二加密的第二解密方法来解密第二内容。解密内容可以由软件执行，第二内容解密单元可以包括防篡改硬件之一和执行防篡改软件的装置。

18. 发明授权

US06677649B2 SRAM cells with two P-well structure 有权
标题翻译：具有两个P阱结构的SRAM单元
公开(公告)号：US06677649B2
公开(公告)日：2004-01-13
申请号：US09565535
申请日：2000-05-05
申请人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
发明人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC分类号： H01L2976
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.
摘要翻译：现有的已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底进行电接触，这将导致不对称性导致了微图案化困难的问题的发生。为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。

19. 发明授权

US06351442B1 Recording medium, recording apparatus and reproduction apparatus with reproduction path flag information 有权
标题翻译：记录介质，记录装置和具有再现路径标志信息的再现装置
公开(公告)号：US06351442B1
公开(公告)日：2002-02-26
申请号：US09323796
申请日：1999-06-01
申请人： Kenji Tagawa , Masataka Minami , Masayuki Kozuka
发明人： Kenji Tagawa , Masataka Minami , Masayuki Kozuka
IPC分类号： G11B390
CPC分类号： G11B27/34 , G06Q20/123 , G07F17/0014 , G11B20/00086 , G11B20/00869 , G11B27/034 , G11B27/105 , G11B27/11 , G11B27/329 , G11B2020/10546 , G11B2220/213 , G11B2220/2512 , G11B2220/2529 , G11B2220/2545 , G11B2220/2562 , G11B2220/41 , G11B2220/61 , G11B2220/65 , H04N5/87 , H04N7/17318 , H04N9/8205 , H04N21/42646 , H04N21/4325 , H04N21/442 , H04N21/47202 , H04N21/4882 , H04N21/6581 , H04N21/8113
摘要： The recording medium of this invention is recorded with a plurality of digital data and a plurality of reproduction path information defining a reproduction order of the plurality of digital data, wherein the plurality of reproduction path information includes first reproduction path information defining a reproduction order of all of the plurality of digital data recorded on the recording medium and second reproduction path information defining a reproduction order of at least one of the plurality of digital data recorded on the recording medium.
摘要翻译：本发明的记录介质用多个数字数据和多个定义多个数字数据的再现顺序的再现路径信息进行记录，其中多个再现路径信息包括定义全部的再现顺序的第一再现路径信息记录在记录介质上的多个数字数据中的多个数字数据中的至少一个数字数据的再现顺序的第二重放路径信息。

20. 发明授权

US09286968B2 Semiconductor integrated circuit device including SRAM cell array and a wiring layer for supplying voltage to well regions of SRAM cells provided on a region exterior of SRAM cell array 有权
标题翻译：包括SRAM单元阵列的半导体集成电路器件和用于向SRAM单元阵列的外部区域上提供的SRAM单元的阱区域提供电压的布线层
公开(公告)号：US09286968B2
公开(公告)日：2016-03-15
申请号：US13616435
申请日：2012-09-14
申请人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
发明人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC分类号： H01L29/76 , H01L27/11 , G11C11/412
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines.
摘要翻译：现有已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底电接触，这将导致不对称性的降低导致微图案化困难。为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。在阵列的中间位置处，与基板平行地形成用于向基板供电的区域。

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