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11. 发明申请

US20100191357A1 PATTERN LAYOUT CREATION METHOD, PROGRAM PRODUCT, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
标题翻译：图案布局创建方法，程序产品和半导体器件制造方法
公开(公告)号：US20100191357A1
公开(公告)日：2010-07-29
申请号：US12630048
申请日：2009-12-03
申请人： Shimon Maeda , Masahiro Miyairi , Soichi Inoue
发明人： Shimon Maeda , Masahiro Miyairi , Soichi Inoue
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A graph in which patterns are each regarded as nodes and nodes of patterns adjacent to each other at a first distance are connected with each other by an edge is produced, each of the patterns is classified into two types so that the two patterns corresponding to the nodes at both ends of the edge are types different to each other, a classification result is corrected by grouping the patterns in each node cluster connected by the edge or each node cluster connected via the node by the edge, and by inverting each of types of a pattern belonging to a same group as that of one pattern, out of a pair of patterns that are classified into a same type and that belong to respectively different groups adjacent to each other at a second distance, and a pattern layout diagram is created based on the corrected classification result.
摘要翻译：每个图形被认为是在第一距离处彼此相邻的图案的节点和节点之间的图形被生成，每个图案被分成两种类型，使得对应于边缘两端的节点是彼此不同的类型，分类结果通过将由边缘连接的每个节点簇中的模式或通过该节点连接的每个节点集合的边缘分组，并将每种类型的在一对图案中属于与一种图案相同的组合的图案，其分为相同类型并且分别属于彼此相邻的第二距离的不同组，并且基于图案布局图对正确的分类结果。

12. 发明申请

US20090031262A1 MASK PATTERN FORMATION METHOD, MASK PATTERN FORMATION APPARATUS, AND LITHOGRAPHY MASK 审中-公开
标题翻译：掩模图案形成方法，掩模图案形成装置和平铺掩模
公开(公告)号：US20090031262A1
公开(公告)日：2009-01-29
申请号：US12179735
申请日：2008-07-25
申请人： Shimon Maeda , Suigen Kyoh , Soichi Inoue
发明人： Shimon Maeda , Suigen Kyoh , Soichi Inoue
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A mask pattern formation method and apparatus capable of performing OPC and lithography verification and obtaining OPC result, and a lithography mask are provided. The method of forming a mask pattern from a design layout of a semiconductor integrated circuit comprises inputting a design layout, performing first OPC on the design layout, calculating a first evaluation value for a finished planar shape of a resist pattern corresponding to the design layout based on the first OPC, determining whether the first evaluation value satisfies a predetermined value, if the first evaluation value does not satisfy the predetermined value, locally altering the design layout, performing second OPC on the altered design layout, calculating a second evaluation value for the altered design layout, performing second determination, and if the second evaluation value satisfies the predetermined value, outputting the result of OPC and the first and second evaluation values.
摘要翻译：提供了能够执行OPC和光刻验证并获得OPC结果的掩模图案形成方法和装置，以及光刻掩模。从半导体集成电路的设计布局形成掩模图案的方法包括输入设计布局，在设计布局上执行第一OPC，计算与设计布局相对应的抗蚀剂图案的成品平面形状的第一评估值在第一OPC上，确定第一评估值是否满足预定值，如果第一评估值不满足预定值，则局部改变设计布局，在改变的设计布局上执行第二OPC，计算第二评估值改变设计布局，执行第二确定，以及如果第二评估值满足预定值，则输出OPC的结果以及第一和第二评估值。

13. 发明授权

US08195697B2 Database creation method, database device and design data evaluation method 有权
标题翻译：数据库创建方法，数据库设备和设计数据评估方法
公开(公告)号：US08195697B2
公开(公告)日：2012-06-05
申请号：US12354594
申请日：2009-01-15
申请人： Shimon Maeda , Noriyuki Honda
发明人： Shimon Maeda , Noriyuki Honda
IPC分类号： G06F7/00
CPC分类号： G06F17/5045
摘要： A database creation method relating to semiconductor ICs, the database registering function block cells constituting a design data of semiconductor IC and evaluation values corresponding to the function block cells such that the function block cells are associated with the evaluation values, for each of the semiconductor ICs, the creation method includes judging whether or not that function block cells constituting a design data of desired semiconductor IC include an unregistered function block cell which is not registered in the database, calculating an unregistered evaluation value corresponding to the unregistered function block cell when the function block cells constituting the design data of the desired semiconductor IC are judged to include the unregistered function block cell, and updating the database by registering the unregistered function block cell and the unregistered evaluation value such that the unregistered function block cell is associated with the unregistered evaluation value.
摘要翻译：关于半导体IC的数据库创建方法，构成半导体IC的设计数据的数据库登记功能块单元和与功能块单元相对应的评估值，使得功能块单元与评估值相关联，用于每个半导体IC 所述创建方法包括判断构成所需半导体IC的设计数据的功能块单元是否包括未登记在数据库中的未注册功能块单元，计算与未注册功能块单元相对应的未注册评估值，判断构成期望的半导体IC的设计数据的块单元包括未注册的功能块单元，并且通过注册未注册的功能块单元和未注册的评估值来更新数据库，使得未注册的功能块单元与未注册的评估相关联价值。

14. 发明授权

US07752595B2 Method for verifying and correcting post-OPC pattern layout 失效
标题翻译： OPC模式布局校验和校正方法
公开(公告)号：US07752595B2
公开(公告)日：2010-07-06
申请号：US11892764
申请日：2007-08-27
申请人： Shimon Maeda , Koujirou Ohyoshi
发明人： Shimon Maeda , Koujirou Ohyoshi
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/70
摘要： A pattern producing method includes specifying a first pattern and a second pattern obtained by modifying the first pattern, specifying a correction area based on the second pattern, in a part of an area including the first pattern and the second pattern, producing at least a part of the first pattern, which is included in the correction area, as a correction target pattern, producing a part of the first or second pattern, which is not included in the correction area, as a correction reference pattern, correcting the correction target pattern on the basis of the correction target pattern and the correction reference pattern, and producing a pattern based on the corrected correction target pattern and the second pattern.
摘要翻译：图案生成方法包括：在包括第一图案和第二图案的区域的一部分中指定通过修改第一图案而获得的第一图案和第二图案，该第一图案和第二图案指定基于第二图案的校正区域，包括在校正区域中的第一图案作为校正目标图案，产生不包括在校正区域中的第一或第二图案的一部分作为校正参考图案，校正校正目标图案校正目标图案和校正参考图案的基础，并且基于校正的校正目标图案和第二图案产生图案。

15. 发明授权

US08151225B2 Pattern layout designing method, semiconductor device manufacturing method, and computer program product 有权
标题翻译：图案布局设计方法，半导体器件制造方法和计算机程序产品
公开(公告)号：US08151225B2
公开(公告)日：2012-04-03
申请号：US12630643
申请日：2009-12-03
申请人： Shimon Maeda
发明人： Shimon Maeda
IPC分类号： G06F17/50 , G06F19/00 , G03F1/00 , G21K5/00
CPC分类号： G06F17/5068 , G03F1/00 , G03F1/26 , G03F1/70
摘要： A graph is created in which mask patterns adjacent to one another at a distance in which desired printing resolution cannot be obtained in a lithography process among mask patterns generated based on a pattern layout design drawing are set as nodes connected to one another by edges. An odd number loop formed by an odd number of nodes is selected from closed loops. When the selected odd number loop is not isolated, based on whether a closed loop group in which a plurality of closed loops including the odd number loop are connected includes an even number loop formed by an even number of nodes, rearrangement target nodes are selected from the odd number loop included in the closed loop group according to different selection references. The layout of patterns described in the pattern layout design drawing is rearranged corresponding to the selected rearrangement target nodes.
摘要翻译：创建图形，其中以基于图案布局设计图形生成的掩模图案之间的光刻处理中在距离不相等的距离处彼此相邻的掩模图案被设置为通过边缘彼此连接的节点。从闭环中选择由奇数个节点形成的奇数循环。当所选择的奇数循环不被隔离时，基于其中包括奇数循环的多个闭环的闭环组是否包括由偶数个节点形成的偶数循环，重排目标节点从根据不同的选择参考，包括在闭环组中的奇数循环。在图案布局设计图中描述的图案的布局对应于所选择的重排目标节点重新排列。

16. 发明申请

US20090053619A1 Pattern producing method, semiconductor device manufacturing method and program 失效
标题翻译：图案生产方法，半导体器件制造方法和程序
公开(公告)号：US20090053619A1
公开(公告)日：2009-02-26
申请号：US11892764
申请日：2007-08-27
申请人： Shimon Maeda , Koujirou Ohyoshi
发明人： Shimon Maeda , Koujirou Ohyoshi
IPC分类号： G03F1/00 , G03F7/20
CPC分类号： G03F1/36 , G03F1/70
摘要： A pattern producing method includes specifying a first pattern and a second pattern obtained by modifying the first pattern, specifying a correction area based on the second pattern, in a part of an area including the first pattern and the second pattern, producing at least a part of the first pattern, which is included in the correction area, as a correction target pattern, producing a part of the first or second pattern, which is not included in the correction area, as a correction reference pattern, correcting the correction target pattern on the basis of the correction target pattern and the correction reference pattern, and producing a pattern based on the corrected correction target pattern and the second pattern.
摘要翻译：图案生成方法包括：在包括第一图案和第二图案的区域的一部分中，指定通过修改第一图案而获得的第一图案和第二图案，该第一图案和第二图案指定基于第二图案的校正区域，包括在校正区域中的第一图案作为校正目标图案，产生不包括在校正区域中的第一或第二图案的一部分作为校正参考图案，校正校正目标图案校正目标图案和校正参考图案的基础，并且基于校正的校正目标图案和第二图案产生图案。

17. 发明授权

US08261214B2 Pattern layout creation method, program product, and semiconductor device manufacturing method 有权
标题翻译：图案布局创建方法，程序产品和半导体器件制造方法
公开(公告)号：US08261214B2
公开(公告)日：2012-09-04
申请号：US12630048
申请日：2009-12-03
申请人： Shimon Maeda , Masahiro Miyairi , Soichi Inoue
发明人： Shimon Maeda , Masahiro Miyairi , Soichi Inoue
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A graph in which patterns are each regarded as nodes and nodes of patterns adjacent to each other at a first distance are connected with each other by an edge is produced, each of the patterns is classified into two types so that the two patterns corresponding to the nodes at both ends of the edge are types different to each other, a classification result is corrected by grouping the patterns in each node cluster connected by the edge or each node cluster connected via the node by the edge, and by inverting each of types of a pattern belonging to a same group as that of one pattern, out of a pair of patterns that are classified into a same type and that belong to respectively different groups adjacent to each other at a second distance, and a pattern layout diagram is created based on the corrected classification result.
摘要翻译：每个图形被认为是在第一距离处彼此相邻的图案的节点和节点之间的图形被生成，每个图案被分成两种类型，使得对应于边缘两端的节点是彼此不同的类型，分类结果通过将由边缘连接的每个节点簇中的模式或通过该节点连接的每个节点集合的边缘分组，并将每种类型的在一对图案中属于与一种图案相同的组合的图案，其分为相同类型并且分别属于彼此相邻的第二距离的不同组，并且基于图案布局图对正确的分类结果。

18. 发明授权

US07966580B2 Process-model generation method, computer program product, and pattern correction method 失效
标题翻译：过程模型生成方法，计算机程序产品和模式校正方法
公开(公告)号：US07966580B2
公开(公告)日：2011-06-21
申请号：US12186244
申请日：2008-08-05
申请人： Shimon Maeda
发明人： Shimon Maeda
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A process-model generation method according to an embodiment of the present invention comprises: forming a test pattern on a film to be processed by exposing a test mask having a mask pattern formed thereon; generating a plurality of process models having a different model parameter; performing a simulation of the mask pattern by using each of the process models to predict a plurality of model patterns; calculating a difference in dimension between the test pattern and each of the model patterns; extracting a model pattern in which the difference in dimension from the test pattern is within a scope of specification from the model patterns; and specifying the process model, which predicts the extracted model pattern, as the mask pattern.
摘要翻译：根据本发明的实施例的工艺模型生成方法包括：通过使形成在其上的掩模图案的测试掩模曝光来在要处理的膜上形成测试图案; 产生具有不同模型参数的多个过程模型; 通过使用每个过程模型来执行掩模图案的模拟以预测多个模型模式; 计算测试图案与每个模型图案之间的尺寸差异; 提取其中尺寸与测试图案的差异在模型范围内的模型模式; 并指定将所提取的模型模式预测为过程模型作为掩模图案。

19. 发明授权

US08785329B2 Method for forming pattern and method for manufacturing semiconductor device 有权
标题翻译：形成图案的方法和制造半导体器件的方法
公开(公告)号：US08785329B2
公开(公告)日：2014-07-22
申请号：US13728495
申请日：2012-12-27
申请人： Shimon Maeda , Kenji Konomi
发明人： Shimon Maeda , Kenji Konomi
IPC分类号： H01L21/00
CPC分类号： H01L21/02318 , B81C1/00031 , B81C2201/0149 , H01L21/0271 , H01L21/32139
摘要： In a method for forming a pattern according to an embodiment, a first guide pattern and a second guide pattern for induced self organization of a DSA material are formed on substrate. On a first DSA condition, a first phase-separated pattern having regularity with respect to the first guide pattern is formed, and a first pattern is formed by processing the lower layer side. Subsequently, on a second DSA condition, a second phase-separated pattern having regularity with respect to the second guide pattern is formed, and a second pattern is formed by processing the lower layer side.
摘要翻译：在根据实施例的形成图案的方法中，在基底上形成用于DSA材料的诱导自组织的第一引导图案和第二引导图案。在第一DSA条件下，形成相对于第一引导图案具有规则性的第一相分离图案，并且通过处理下层侧形成第一图案。随后，在第二DSA条件下，形成相对于第二引导图案具有规则性的第二相分离图案，并且通过处理下层侧形成第二图案。

20. 发明申请

US20060285739A1 Evaluation pattern generating method and computer program product 审中-公开
标题翻译：评估模式生成方法和计算机程序产品
公开(公告)号：US20060285739A1
公开(公告)日：2006-12-21
申请号：US11448719
申请日：2006-06-08
申请人： Shimon Maeda
发明人： Shimon Maeda
IPC分类号： G06K9/00 , G06F17/50
CPC分类号： G06K9/6255 , G03F1/36 , G03F1/68
摘要： An evaluation pattern generating method includes generating plural types of unit patterns based on a seed pattern group and a unit frame, the seed pattern group including plural types of seed patterns, each of the plural types of unit patterns including a pattern that corresponds to the seed pattern arranged in the unit frame, and generating plural types of evaluation patterns based on the plural types of unit patterns and an arrangement frame having a size that is N times of the unit frame (N is a positive integer), each of the plural types of evaluation patterns including the plural types of evaluation unit patterns arranged in the arrangement frame so that the inside of the arrangement frame is filled with the plural types of the unit patterns.
摘要翻译：评估模式生成方法包括基于种子图案组和单位框架生成多种类型的单位图案，种子图案组包括多种种子图案，多种类型的单位图案中的每一种包括与种子对应的图案模式，并且基于多种类型的单位图形生成多种类型的评估模式，并且生成尺寸为单位框架的N倍的排列框（N为正整数），多种类型包括布置在布置框架中的多种类型的评估单元图案的评估图案，使得布置框架的内部填充有多种类型的单元图案。

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