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11. 发明授权

US6154868A Method and means for computationally efficient on-the-fly error correction in linear cyclic codes using ultra-fast error location 失效
标题翻译：用于使用超快速误差位置的线性循环码中计算高效的即时纠错的方法和装置
公开(公告)号：US6154868A
公开(公告)日：2000-11-28
申请号：US896348
申请日：1997-07-18
申请人： Charles Edwin Cox , Myron Dale Flickner , James Lee Hafner , Martin Aureliano Hassner , Barry Marshall Trager , Shmuel Winograd
发明人： Charles Edwin Cox , Myron Dale Flickner , James Lee Hafner , Martin Aureliano Hassner , Barry Marshall Trager , Shmuel Winograd
IPC分类号： H03M13/00 , H03M13/15
CPC分类号： H03M13/1545 , H03M13/1515 , H03M13/616
摘要： A computationally efficient, machine-implementable method and means for detecting and correcting errors in received codewords on-the-fly within the capacity of a linear cyclic code using ultra-fast error location processing. Each error locator polynomial of degree t over a finite Galois field derived from a codeword syndrome is mapped into a matrix representative of a system of linear simultaneous equations related to the polynomial coefficients. Roots indicative of error locations within the codeword are extracted from the matrix by a modified Gaussian Elimination process for all the roots where t.ltoreq.5 and at least one root plus a subset of candidate roots from the finite field for iterative substitution where t>5. Corrected values are separately determined and correction is secured by logically combining the corrected values with the codeword values in error at the error locations represented by the roots.
摘要翻译：一种计算有效的机器可实现的方法和装置，用于使用超快速错误位置处理在线性循环码的容量内即时检测和纠正接收到的码字中的错误。将来自码字综合征的有限伽罗瓦域的度t的每个误差定位多项式映射成表示与多项式系数相关的线性联立方程组的矩阵。指示码字内的错误位置的根通过对于t 5的所有根的修正的高斯消除过程从矩阵中提取，并且至少一个根加上来自用于迭代取代的有限域的候选根的子集，其中t> 5。单独确定校正后的值，并且通过将修正的值与由根表示的错误位置处的错误的码字值进行逻辑组合来确保校正。

12. 发明授权

US6141786A Method and apparatus for performing arithmetic operations on Galois fields and their extensions 失效
标题翻译：用于对伽罗瓦域及其扩展进行算术运算的方法和装置
公开(公告)号：US6141786A
公开(公告)日：2000-10-31
申请号：US90511
申请日：1998-06-04
申请人： Charles Edwin Cox , Martin Aureliano Hassner , Barry Marshall Trager , Shmuel Winograd
发明人： Charles Edwin Cox , Martin Aureliano Hassner , Barry Marshall Trager , Shmuel Winograd
IPC分类号： H03M13/15 , G11C29/00
CPC分类号： H03M13/158 , H03M13/15 , H03M13/1515
摘要： The invention relates to an arithmetic unit (AU) in combination with an algebraic block ECC decoder for controlling errors in an electronically recorded digital data message by performing at least one of a plurality of predetermined arithmetic operations on the data message in one or more of a plurality of subfields of a first GF(2.sup.12) or a second GF(2.sup.8) finite field. The arithmetic operations are selected either from a first group of operations associated with a first subfield GF(2.sup.4) as cubically extended to the first finite field GF(2.sup.12) or as quadratically extended to the second finite field GF(2.sup.8), or selected from a second group of operations associated with a second subfield GF(2.sup.6) as quadratically extended to the first finite field GF(2.sup.12).
摘要翻译：本发明涉及一种与代数块ECC解码器组合的算术单元（AU），用于通过对数字消息中的一个或多个中的数据消息执行多个预定算术运算中的至少一个来控制电子记录数字数据消息中的错误，第一GF（212）或第二GF（28）有限域的多个子场。算术运算从与第一子场GF（24）相关联的第一组运算中选择为立方式扩展到第一有限域GF（212）或二次扩展到第二有限域GF（28），或从与第二子场GF（26）相关联的第二组操作，其被二次扩展到第一有限域GF（212）。

13. 发明授权

US09128868B2 System for error decoding with retries and associated methods 有权
标题翻译：用于通过重试和相关方法进行错误解码的系统
公开(公告)号：US09128868B2
公开(公告)日：2015-09-08
申请号：US12023356
申请日：2008-01-31
申请人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd
发明人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd
IPC分类号： G06F11/08 , G06F11/14 , H04W28/04 , H04W4/00 , G06F11/10
CPC分类号： G06F11/1044 , G06F11/08 , G06F11/14 , H04W4/00 , H04W28/04
摘要： A system to improve error code decoding with retries may include a processing unit that requests data packets, and a queue to hold the data packets for the processing unit. The system may also include a decoder to determine a processing time for each data packet in the queue based upon any errors in each data packet, and if the processing time for a particular data packet is greater than a threshold, then to renew any requests for the data packets that are in the queue.
摘要翻译：通过重试来改进错误代码解码的系统可以包括请求数据分组的处理单元和用于保存用于处理单元的数据分组的队列。系统还可以包括解码器，用于基于每个数据分组中的任何错误来确定队列中每个数据分组的处理时间，并且如果特定数据分组的处理时间大于阈值，则更新对于队列中的数据包。

14. 发明授权

US08615689B2 Correcting errors in longitudinal position (LPOS) words 有权
标题翻译：校正纵向位置误差（LPOS）词
公开(公告)号：US08615689B2
公开(公告)日：2013-12-24
申请号：US13612396
申请日：2012-09-12
申请人： William J. Kabelac , Barry M. Trager , Shmuel Winograd
发明人： William J. Kabelac , Barry M. Trager , Shmuel Winograd
IPC分类号： G11C29/00
CPC分类号： G11B27/107 , G11B27/24 , G11B27/36 , G11B2220/93
摘要： A method for longitudinal position (LPOS) detection in a magnetic tape storage system for storing data upon linear tape open (LTO) magnetic storage tape, which data includes odd and even 36-bit LPOS words with error correcting ability. The method includes first encoding positional information onto the tape within the 36-bit LPOS words using each LPOS word's 8-bit sync mark field, and six of each LPOS word's 4-bit symbol fields, wherein 6 of 24 total bits comprise the encoded 8-bit sync mark field: Sy, and six 4-bit symbol fields are utilized as parity bits. The magnetic tape storage system passes the LTO magnetic storage tape encoded with the odd and even LPOS words with error correcting ability longitudinally across a servo reader/writer at a known speed, decoding the encoded positional information and detecting and correcting both ambiguous bits and single erroneous bit errors.
摘要翻译：一种用于在线性磁带打开（LTO）磁存储磁带上存储数据的磁带存储系统中的纵向位置（LPOS）检测方法，该数据包括具有纠错能力的奇数和偶数36位LPOS字。该方法包括使用每个LPOS字的8位同步标记字段以及每个LPOS字的4位符号字段中的六个，在36位LPOS字中的位置信息之上编码位置信息，其中24个总比特中的6个包括编码的8 位同步标记字段：Sy和六个4位符号字段用作奇偶校验位。磁带存储系统以已知速度将穿过伺服读取器/写入器的具有纠错能力的奇数和偶数LPOS字编码的LTO磁存储带纵向跨越伺服读取器/写入器，对编码的位置信息进行解码，并检测和校正两个不明确的位和单个错误位错误。

15. 发明申请

US20130198705A1 CIRCUIT VERIFICATION USING COMPUTATIONAL ALGEBRAIC GEOMETRY 有权
标题翻译：使用计算代数几何的电路验证
公开(公告)号：US20130198705A1
公开(公告)日：2013-08-01
申请号：US13360083
申请日：2012-01-27
申请人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
发明人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.
摘要翻译：在本发明的一个示例性实施例中，一种方法包括：接收对要对其进行验证的多个输入的操作的电路的第一描述; 接收对所述电路的预期行为的第二描述，其中所述第二描述中的预期行为被表示为在至少一个伽罗瓦域上的多变量多项式的代数系统集合; 将至少一个计算代数几何技术应用于第一描述和第二描述的组合以确定电路是否被验证，其中电路的验证确认基于第一描述获得的至少一个输出对应于至少一个预期的基于在第二描述中表达的预期行为的价值; 并且输出关于电路是否被验证的指示。

16. 发明授权

US08352806B2 System to improve memory failure management and associated methods 失效
标题翻译：系统改善内存故障管理及相关方法
公开(公告)号：US08352806B2
公开(公告)日：2013-01-08
申请号：US12023498
申请日：2008-01-31
申请人： Marc A. Gollub , Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Shmuel Winograd , Kenneth L. Wright
发明人： Marc A. Gollub , Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Shmuel Winograd , Kenneth L. Wright
IPC分类号： G06F11/00
CPC分类号： H03M13/1545 , G06F11/1048 , H03M13/1515 , H03M13/154 , H03M13/353 , H03M13/3707 , H03M13/6511
摘要： A system to improve memory failure management may include memory, and an error control decoder to determine failures in the memory. The system may also include an agent that may monitor failures in the memory. The system may further include a table where the error control decoder may record the failures, and where the agent can read and write to.
摘要翻译：改善存储器故障管理的系统可以包括存储器和用于确定存储器中的故障的错误控制解码器。系统还可以包括可以监视存储器中的故障的代理。该系统还可以包括一个表，其中错误控制解码器可以记录故障，以及代理可以在哪里读写。

17. 发明授权

US08176391B2 System to improve miscorrection rates in error control code through buffering and associated methods 失效
标题翻译：系统通过缓冲和相关方法提高错误控制代码中的错误率
公开(公告)号：US08176391B2
公开(公告)日：2012-05-08
申请号：US12023516
申请日：2008-01-31
申请人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/00
CPC分类号： G06F11/1044
摘要： A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.
摘要翻译：用于改善错误控制代码中的错误率的系统可以包括处理至少两个数据分组的具有安全解码模式的错误控制解码器。系统还可以包括缓冲器，以从误差控制解码器接收经处理的至少两个数据分组。误差控制解码器可以对与至少两个数据分组的处理相关的不可校正误差信号应用逻辑或运算，以产生全局不可校正的误差信号。系统还可以包括接收器以接收至少两个数据分组和全局不可校正的误差信号。

18. 发明授权

US08640065B2 Circuit verification using computational algebraic geometry 有权
标题翻译：使用计算代数几何的电路验证
公开(公告)号：US08640065B2
公开(公告)日：2014-01-28
申请号：US13360083
申请日：2012-01-27
申请人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
发明人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/504
摘要： In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.
摘要翻译：在本发明的一个示例性实施例中，一种方法包括：接收对要对其进行验证的多个输入的操作的电路的第一描述; 接收对所述电路的预期行为的第二描述，其中所述第二描述中的预期行为被表示为在至少一个伽罗瓦域上的多变量多项式的代数系统集合; 将至少一个计算代数几何技术应用于第一描述和第二描述的组合以确定电路是否被验证，其中电路的验证确认基于第一描述获得的至少一个输出对应于至少一个预期的基于在第二描述中表达的预期行为的价值; 并且输出关于电路是否被验证的指示。

19. 发明申请

US20120005561A1 REDUCED CIRCUIT IMPLEMENTATION OF ENCODER AND SYNDROME GENERATOR 有权
标题翻译：编码器和综合发生器的减少电路实现
公开(公告)号：US20120005561A1
公开(公告)日：2012-01-05
申请号：US13168559
申请日：2011-06-24
申请人： Barry M. Trager , Shmuel Winograd
发明人： Barry M. Trager , Shmuel Winograd
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： H03M13/1515 , H03M13/1595
摘要： An error correction method and system includes an Encoder and Syndrome-generator that operate in parallel to reduce the amount of circuitry used to compute check symbols and syndromes for error correcting codes. The system and method computes the contributions to the syndromes and check symbols 1 bit at a time instead of 1 symbol at a time. As a result, the even syndromes can be computed as powers of the odd syndromes. Further, the system assigns symbol addresses so that there are, for an example GF(28) which has 72 symbols, three (3) blocks of addresses which differ by a cube root of unity to allow the data symbols to be combined for reducing size and complexity of odd syndrome circuits. Further, the implementation circuit for generating check symbols is derived from syndrome circuit using the inverse of the part of the syndrome matrix for check locations.
摘要翻译：错误校正方法和系统包括编码器和综合发生器，其并行操作以减少用于计算用于纠错码的校验符号和校正子的电路的数量。系统和方法一次计算对一致性的贡献和一次检查符号，而不是1个符号。因此，偶数综合征可以计算为奇数综合征的功率。此外，系统分配符号地址，使得对于具有72个符号的示例GF（28），具有不同于单位的立方根的三（3）个地址块，以允许数据符号被组合以减小大小和奇异综合征电路的复杂性。此外，用于产生检查符号的实现电路是使用校正位置的校正子矩阵的部分的倒数从校正子电路导出的。

20. 发明申请

US20100299576A1 System to Improve Miscorrection Rates in Error Control Code Through Buffering and Associated Methods 失效
标题翻译：系统通过缓冲和相关方法提高错误控制代码的误码率
公开(公告)号：US20100299576A1
公开(公告)日：2010-11-25
申请号：US12023516
申请日：2008-01-31
申请人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1044
摘要： A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.
摘要翻译：用于改善错误控制代码中的错误率的系统可以包括处理至少两个数据分组的具有安全解码模式的错误控制解码器。系统还可以包括缓冲器，以从误差控制解码器接收经处理的至少两个数据分组。误差控制解码器可以对与至少两个数据分组的处理相关的不可校正误差信号应用逻辑或运算，以产生全局不可校正的误差信号。系统还可以包括接收器以接收至少两个数据分组和全局不可校正的误差信号。

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