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11. 发明授权

US06054385A Elevated local interconnect and contact structure 失效
标题翻译：高架局部互连和接触结构
公开(公告)号：US06054385A
公开(公告)日：2000-04-25
申请号：US792086
申请日：1997-01-31
申请人： Mark I. Gardner , Fred Hause
发明人： Mark I. Gardner , Fred Hause
IPC分类号： H01L21/768 , H01L21/283
CPC分类号： H01L21/76895
摘要： A semiconductor process in which a local interconnect, formed above a first transistor level, is connected to the first transistor level through a self-aligned and low resistivity contact structure. A semiconductor substrate is provided and a first transistor level formed on an upper surface of the semiconductor substrate. The first transistor level includes a first transistor. A local interconnect is then formed over the first transistor level. The local interconnect is vertically displaced above the first transistor level such that the local interconnect may traverse a gate of the first transistor without contacting the gate. A contact structure is then formed to connect the first source/drain structure of the first transistor with the local interconnect. The contact structure includes a first self-aligned silicide at an interface between the contact structure and the first source/drain region and further includes a second self-aligned silicide at an interface between the contact structure and the local interconnect.
摘要翻译：形成在第一晶体管级上方的局部互连通过自对准和低电阻率接触结构连接到第一晶体管级的半导体工艺。提供半导体衬底，并且形成在半导体衬底的上表面上的第一晶体管级。第一晶体管电平包括第一晶体管。然后在第一晶体管级上形成局部互连。局部互连在第一晶体管电平之上垂直位移，使得局部互连可以穿过第一晶体管的栅极而不接触栅极。然后形成接触结构以将第一晶体管的第一源极/漏极结构与局部互连连接。接触结构包括在接触结构和第一源极/漏极区之间的界面处的第一自对准硅化物，并且还包括在接触结构和局部互连之间的界面处的第二自对准硅化物。

12. 发明授权

US5827763A Method of forming a multiple transistor channel doping using a dual resist fabrication sequence 失效
标题翻译：使用双抗蚀剂制造顺序形成多晶体管沟道掺杂的方法
公开(公告)号：US5827763A
公开(公告)日：1998-10-27
申请号：US791378
申请日：1997-01-30
申请人： Mark I. Gardner , Fred Hause
发明人： Mark I. Gardner , Fred Hause
IPC分类号： H01L21/266 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823412 , H01L21/266
摘要： A method of forming a multiple transistor channel doping in a semiconductor substrate utilizes a unique photoresist sequence. A pattern of a first resist in first and second locations on first and second different areas of the semiconductor substrate is formed, respectively. A pattern of a second resist is then formed on the second area, wherein the second resist covers the first resist pattern in the second location. The first resist is selected for being immune from the second resist. Ions are then implanted in the first area to form a first conductivity type well having a first multiple transistor channel doping profile. The second resist pattern is then removed and a pattern of a third resist is formed on the first area, wherein the third resist covers the first resist pattern in the first location. In addition, the first resist is selected for being immune from the third resist. Lastly, ions are implanted in the second area to form a second conductivity type well having a second multiple transistor channel doping profile. A substrate having a multiple transistor channel doping profile is also disclosed.
摘要翻译：在半导体衬底中形成多晶体管沟道掺杂的方法利用独特的光刻胶序列。分别形成在半导体衬底的第一和第二不同区域上的第一和第二位置中的第一抗蚀剂的图案。然后在第二区域上形成第二抗蚀剂的图案，其中第二抗蚀剂在第二位置覆盖第一抗蚀剂图案。选择第一抗蚀剂以免受第二抗蚀剂的侵害。然后将离子注入第一区域以形成具有第一多晶体管沟道掺杂分布的第一导电类型阱。然后去除第二抗蚀剂图案，并且在第一区域上形成第三抗蚀剂的图案，其中第三抗蚀剂在第一位置覆盖第一抗蚀剂图案。此外，选择第一抗蚀剂以免受第三抗蚀剂的侵害。最后，离子注入第二区域以形成具有第二多晶体管沟道掺杂分布的第二导电类型阱。还公开了具有多晶体管沟道掺杂分布的衬底。

13. 发明授权

US5763311A High performance asymmetrical MOSFET structure and method of making the same 失效
标题翻译：高性能非对称MOSFET结构及其制作方法
公开(公告)号：US5763311A
公开(公告)日：1998-06-09
申请号：US743522
申请日：1996-11-04
申请人： Mark I. Gardner , Daniel Kadosh , Fred Hause
发明人： Mark I. Gardner , Daniel Kadosh , Fred Hause
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66659 , H01L29/7835 , H01L29/6656 , Y10S257/90
摘要： A method of fabricating a high performance asymmetrical field effect transistor (FET) includes the steps of forming a gate oxide and a gate electrode on a layer of semiconductor material of a first conductivity type. The gate electrode includes a first side edge adjacent a first region of the semiconductor material and a second side edge proximate a second region of the semiconductor material. First and second lightly doped regions are formed in regions of the semiconductor material not covered by the gate oxide, and extending away from the first and second side edges of the gate electrode, respectively. First and second sidewall spacers are formed proximate the first and second side edges of the gate electrode, respectively, each sidewall spacer including a composite sidewall spacer of a first and a second spacer material. Lastly, a very highly doped source region and a highly doped drain region are formed in the first and second regions, respectively, the very highly doped source region having a greater dopant concentration of the second conductivity type than the highly doped drain region and the highly doped drain region having a dopant concentration greater than the lightly doped region extending away from the second side edge of said gate electrode. A novel FET is disclosed also.
摘要翻译：制造高性能不对称场效应晶体管（FET）的方法包括在第一导电类型的半导体材料层上形成栅极氧化物和栅电极的步骤。栅电极包括与半导体材料的第一区域相邻的第一侧边缘和靠近半导体材料的第二区域的第二侧边缘。第一和第二轻掺杂区域形成在半导体材料未被栅极氧化物覆盖的区域中，并且分别从栅电极的第一和第二侧边缘延伸。第一和第二侧壁间隔物分别形成在栅电极的第一和第二侧边缘附近，每个侧壁间隔物包括第一和第二间隔物材料的复合侧壁间隔物。最后，分别在第一和第二区域中形成非常高掺杂的源极区和高掺杂的漏极区，非常高掺杂的源极区具有比高掺杂漏极区高的掺杂浓度的第二导电类型，掺杂浓度的漏极区域的掺杂浓度大于远离所述栅电极的第二侧边缘延伸的轻掺杂区域。还公开了一种新颖的FET。

14. 发明授权

US6148832A Method and apparatus for in-situ cleaning of polysilicon-coated quartz furnaces 失效
标题翻译：用于多晶硅涂层石英炉原位清洗的方法和装置
公开(公告)号：US6148832A
公开(公告)日：2000-11-21
申请号：US145606
申请日：1998-09-02
申请人： Mark C. Gilmer , Mark I. Gardner , Robert Paiz
发明人： Mark C. Gilmer , Mark I. Gardner , Robert Paiz
IPC分类号： B08B9/093 , C11D7/08 , C11D7/32 , C11D7/50 , C11D11/00 , B08B3/02 , B08B9/00
CPC分类号： C11D7/08 , B08B9/093 , C11D11/0041 , C11D7/5013 , C11D7/3209
摘要： An apparatus for in-situ cleaning of polysilicon-coated quartz furnaces are presented. Traditionally, disassembling and reassembling the furnace is required to clean the quartz. This procedure requires approximately four days of down time which can be very costly for a company. In addition, cleaning the quartz requires large baths filled with a cleaning agent. These baths occupy a large amount of laboratory space and require a large amount of the cleaning agent. Cleaning the furnace in-situ eliminates the very time consuming procedure of assembling and disassembling the furnace and at the same time requires less laboratory space and less amount of cleaning agent. The polysilicon remover may be either a mixture of hydrofluoric and nitric acid or TMAH. TMAH is preferred because it less hazardous than hydrofluoric acid and compatible with more materials. The cleaning agent may be introduced into the furnace either from the built-in injectors or from additionally installed injectors. If the built-in injectors are used, the input system of the furnace is cleaned in addition to the quartz inner lining.
摘要翻译：介绍了一种用于原位清洗多晶硅涂层石英炉的设备。传统上，需要拆卸和重新组装炉子来清洁石英。该程序需要大约四天的停机时间，这对公司来说可能是非常昂贵的。此外，清洁石英需要大量的填充有清洁剂的浴池。这些浴室占据大量的实验室空间，需要大量的清洁剂。原地清洗炉子消除了组装和拆卸炉子非常耗时的过程，同时需要更少的实验室空间和更少量的清洁剂。多晶硅去除剂可以是氢氟酸和硝酸或TMAH的混合物。 TMAH是优选的，因为它比氢氟酸更危险，并且与更多的材料相容。清洁剂可以从内置注射器或另外安装的注射器引入炉中。如果使用内置注射器，除了石英内衬之外，还要清洁炉子的输入系统。

15. 发明授权

US5918133A Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof 失效
标题翻译：半导体器件沿着沟道具有双栅极电介质厚度及其制造
公开(公告)号：US5918133A
公开(公告)日：1999-06-29
申请号：US993029
申请日：1997-12-18
申请人： Mark I. Gardner , Robert Paiz
发明人： Mark I. Gardner , Robert Paiz
IPC分类号： H01L21/265 , H01L21/28 , H01L21/32 , H01L21/336 , H01L29/423 , H01L29/51 , H01L21/31 , H01L21/3115
CPC分类号： H01L21/28202 , H01L21/26506 , H01L21/2822 , H01L21/32 , H01L29/42368 , H01L29/512 , H01L29/518 , H01L29/66659 , H01L21/28194
摘要： Generally, the present invention relates to a semiconductor device having a dual thickness gate dielectric along the channel and a process of fabricating such a device. By providing a dual thickness gate dielectric, the gate dielectric can, for example, be optimized to the transistor and device performance can be enhanced.
摘要翻译：通常，本发明涉及一种具有沿通道的双重厚度栅极电介质的半导体器件和制造这种器件的工艺。通过提供双厚度栅极电介质，栅极电介质例如可以优化到晶体管，并且可以提高器件性能。

16. 发明授权

US06214123B1 Chemical vapor deposition systems and methods for depositing films on semiconductor wafers 失效
标题翻译：化学气相沉积系统和在半导体晶片上沉积薄膜的方法
公开(公告)号：US06214123B1
公开(公告)日：2001-04-10
申请号：US09137902
申请日：1998-08-20
申请人： Mark I. Gardner , Mark C. Gilmer , Robert Paiz
发明人： Mark I. Gardner , Mark C. Gilmer , Robert Paiz
IPC分类号： C23C1600
CPC分类号： C23C16/45514 , C23C16/4409 , C23C16/4584
摘要： The present disclosure relates to a chemical vapor deposition system including a chemical vapor deposition chamber, and a circlet wafer positioned within the chemical vapor deposition chamber. The circlet wafer is mounted on a rotatable member that at least partially extends through an opening of the wafer. A drive mechanism is used to rotate the rotatable member and the circlet wafer. The system also includes a gas injector for injecting reactive gases toward the circlet wafer. The present disclosure also relates to a chemical vapor deposition system including a chemical vapor deposition chamber, a wafer positioned within the chemical vapor deposition chamber, and a gas injector for injecting first and second reactive gases toward the wafer. The gas injector includes a mixing region for mixing the first and second reactive gases before the first and second reactive gases are discharged from the gas injector.
摘要翻译：本公开涉及包括化学气相沉积室和位于化学气相沉积室内的圆盘晶片的化学气相沉积系统。小圆片安装在至少部分地延伸穿过晶片的开口的可旋转构件上。使用驱动机构来旋转可旋转构件和小圆片。该系统还包括用于将反应性气体注入到小圆片的气体注射器。本公开还涉及包括化学气相沉积室，位于化学气相沉积室内的晶片的化学气相沉积系统和用于向晶片注入第一和第二反应气体的气体注入器。气体喷射器包括用于在第一和第二反应气体从气体喷射器排出之前混合第一和第二反应气体的混合区域。

17. 发明授权

US6140191A Method of making high performance MOSFET with integrated simultaneous formation of source/drain and gate regions 有权
标题翻译：制造高性能MOSFET的方法，集成同时形成源极/漏极和栅极区域
公开(公告)号：US6140191A
公开(公告)日：2000-10-31
申请号：US157973
申请日：1998-09-21
申请人： Mark I. Gardner , Mark C. Gilmer , Robert Paiz
发明人： Mark I. Gardner , Mark C. Gilmer , Robert Paiz
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238
CPC分类号： H01L29/66575 , H01L21/823814 , H01L21/823842 , H01L21/2652 , H01L29/66545
摘要： An integrated circuit and a method of making a transistor thereof are provided. The method includes the steps of forming a first stack on the substrate and a second stack on substrate in spaced-apart relation to the first stack, where the first stack has a first layer and first and second spacers adjacent to the first layer and the second stack has a second layer and third and fourth spacers adjacent to the second layer. A gate dielectric layer is formed on the substrate between the first and second stacks and a first conductor layer is formed on the gate dielectric layer. A first source/drain region is formed beneath the first conductor layer and a second source/drain region is formed beneath the second conductor layer. The first and second layers are removed and a first contact is formed on the first source/drain region and a second contact is formed on the second source/drain region. The method integrates gate and source/drain region formation and provides for gate electrodes with work functions tailored for n-channel and p-channel devices.
摘要翻译：提供集成电路及其制造晶体管的方法。该方法包括以下步骤：在衬底上形成第一堆叠，并且在衬底上形成与第一堆叠间隔开的第二叠层，其中第一堆叠具有第一层，第一和第二衬垫与第一层相邻，堆叠具有与第二层相邻的第二层和第三和第四间隔物。在第一和第二堆叠之间的衬底上形成栅极电介质层，并且在栅极电介质层上形成第一导体层。第一源极/漏极区域形成在第一导体层下面，并且第二源极/漏极区域形成在第二导体层下面。去除第一层和第二层，并且在第一源极/漏极区上形成第一接触，并且在第二源极/漏极区上形成第二接触。该方法集成了栅极和源极/漏极区域形成，为门极提供了针对n沟道和p沟道器件定制的工作功能。

18. 发明授权

US6037244A Method of manufacturing a semiconductor device using advanced contact formation 失效
标题翻译：使用高级接触形成制造半导体器件的方法
公开(公告)号：US6037244A
公开(公告)日：2000-03-14
申请号：US821660
申请日：1997-03-19
申请人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz , Frederick N. Hause , Sey-Ping Sun
发明人： Mark I. Gardner , Thomas E. Spikes, Jr. , Robert Paiz , Frederick N. Hause , Sey-Ping Sun
IPC分类号： H01L21/768 , H01L21/28 , H01L21/31
CPC分类号： H01L21/76895 , H01L21/76807
摘要： A method of forming a semiconductor device by using a pillar to form a contact with an active region of the device. A semiconductor device is formed by forming one or more active regions on a substrate of the semiconductor device and forming a pillar over at least a portion of one of the active regions. An insulating film selective to the pillar is provided over portions of the substrate adjacent the pillar. The pillar is then used to form a conductive contact with the active region over which it is formed. In one embodiment, the pillar is formed from a photoresist, while in other embodiments, the pillar is formed from a conductor material such as a metal. The active region may form a source/drain region or a gate electrode.
摘要翻译：一种通过使用柱形成与器件的有源区的接触形成半导体器件的方法。通过在半导体器件的衬底上形成一个或多个有源区并在一个有源区的至少一部分上形成柱来形成半导体器件。在基板的邻近柱的部分上设置对柱子有选择性的绝缘膜。然后使用该柱与其形成的有源区形成导电接触。在一个实施例中，柱由光致抗蚀剂形成，而在其它实施例中，柱由诸如金属的导体材料形成。有源区可以形成源/漏区或栅电极。

19. 发明授权

US5970350A Semiconductor device having a thin gate oxide and method of manufacture thereof 失效
标题翻译：具有薄栅极氧化物的半导体器件及其制造方法
公开(公告)号：US5970350A
公开(公告)日：1999-10-19
申请号：US760723
申请日：1996-12-05
申请人： Mark I. Gardner , Thomas, Jr. E. Spikes , Robert Paiz
发明人： Mark I. Gardner , Thomas, Jr. E. Spikes , Robert Paiz
IPC分类号： H01L21/265 , H01L21/28 , H01L29/51 , H01L21/336
CPC分类号： H01L21/28185 , H01L21/26506 , H01L21/2822 , H01L29/518
摘要： A process for fabricating a device having a thin gate oxide layer on which a gate electrode is formed is disclosed. The thin gate oxide layer is formed using an ion implantation process in order to reliably control the thickness of the gate oxide layer. A nitrogen-containing species is used in the ion implantation in order to form a nitrogen rich oxide layer and to increase the reliability and performance of a resultant device.
摘要翻译：公开了一种制造具有形成栅电极的薄栅氧化层的器件的工艺。为了可靠地控制栅氧化层的厚度，使用离子注入工艺形成薄栅氧化层。在离子注入中使用含氮物质以形成富氮氧化物层并提高所得装置的可靠性和性能。

20. 发明授权

US06727569B1 Method of making enhanced trench oxide with low temperature nitrogen integration 失效
标题翻译：制备具有低温氮一体化的增强型沟槽氧化物的方法
公开(公告)号：US06727569B1
公开(公告)日：2004-04-27
申请号：US09063081
申请日：1998-04-21
申请人： Mark I. Gardner , Mark C. Gilmer , Robert Paiz
发明人： Mark I. Gardner , Mark C. Gilmer , Robert Paiz
IPC分类号： H01L2900
CPC分类号： H01L21/76235
摘要： A structure and an improved isolation trench between active regions within the semiconductor substrate involves forming on a silicon substrate and forming a nitride layer on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into a portion of the trench liner to form an oxynitride layer. After formation of the oxynitride layer, the trench is filled with a dielectric preferably comprised of a CVD oxide. Thereafter, the CVD fill dielectric is planarized and the nitride layer is stripped away.
摘要翻译：半导体衬底内的有源区域之间的结构和改进的隔离沟槽包括在硅衬底上形成并在衬垫层上形成氮化物层。此后，在氮化硅层上图案化光致抗蚀剂层，使得随后将形成隔离沟槽的氮化物层的区域被暴露。接下来，蚀刻掉位于氮化物层的暴露区域之下的氮化物层和焊盘层的暴露区域以暴露硅衬底的区域。随后，用干蚀刻工艺将隔离沟槽蚀刻到硅衬底中。然后形成沟槽衬垫，并且氮结合到沟槽衬垫的一部分中以形成氧氮化物层。在形成氮氧化物层之后，用优选由CVD氧化物构成的电介质填充沟槽。此后，CVD填充电介质被平坦化，并且氮化物层被剥离。

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