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11. 发明申请

US20050070057A1 Semiconductor layer formation 失效
标题翻译：半导体层形成
公开(公告)号：US20050070057A1
公开(公告)日：2005-03-31
申请号：US10919784
申请日：2004-08-17
申请人： Chun-Li Liu , Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White , Qianghua Xie
发明人： Chun-Li Liu , Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White , Qianghua Xie
IPC分类号： H01L20060101 , H01L21/00 , H01L21/338
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A process for forming strained semiconductor layers. The process include flowing a chlorine bearing gas (e.g. hydrogen chloride, chlorine, carbon tetrachloride, and trichloroethane) over the wafer while heating the wafer. In one example, the chorine bearing gas is flowed during a condensation process on a semiconductor layer that is used as a template layer for forming a strain semiconductor layer (e.g. strain silicon). In other examples, the chlorine bearing gas is flowed during a post bake of the wafer after the condensation operation.
摘要翻译：一种形成应变半导体层的工艺。该方法包括在加热晶片的同时使含氯气体（例如氯化氢，氯气，四氯化碳和三氯乙烷）流过晶片。在一个实例中，在用作形成应变半导体层（例如应变硅）的模板层的半导体层上的冷凝过程中，含有轴承气体流动。在其他实例中，在冷凝操作之后，在晶片的后烘烤期间，含氯气体流动。

12. 发明申请

US20050070053A1 Template layer formation 有权
标题翻译：模板层形成
公开(公告)号：US20050070053A1
公开(公告)日：2005-03-31
申请号：US10919922
申请日：2004-08-17
申请人： Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Ted White
发明人： Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Ted White
IPC分类号： H01L20060101 , H01L21/00 , H01L21/338
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A process for forming a strained semiconductor layer. The process includes implanting ions into a semiconductor layer prior to performing a condensation process on the layer. The ions assist in diffusion of atoms (e.g. germanium) in the semiconductor layer and to increase the relaxation of the semiconductor layer. After the condensation process, the layer can be used as a template layer for forming a strained semiconductor layer.
摘要翻译：一种形成应变半导体层的工艺。该方法包括在层之前进行冷凝过程之前将离子注入到半导体层中。离子有助于半导体层中的原子（例如锗）的扩散并增加半导体层的松弛。在冷凝过程之后，该层可用作形成应变半导体层的模板层。

13. 发明申请

US20070190745A1 Method to selectively form regions having differing properties and structure 有权
公开(公告)号：US20070190745A1
公开(公告)日：2007-08-16
申请号：US11351518
申请日：2006-02-10
申请人： Mariam Sadaka , Bich-Yen Nguyen , Voon-Yew Thean , Ted White
发明人： Mariam Sadaka , Bich-Yen Nguyen , Voon-Yew Thean , Ted White
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/823807 , H01L21/76264 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , Y10S438/973
摘要： A semiconductor device is formed having two physically separate regions with differing properties such as different surface orientation, crystal rotation, strain or composition. In one form a first layer having a first property is formed on an insulating layer. The first layer is isolated into first and second physically separate areas. After this physical separation, only the first area is amorphized. A donor wafer is placed in contact with the first and second areas. The semiconductor device is annealed to modify the first of the first and second separate areas to have a different property from the second of the first and second separate areas. The donor wafer is removed and at least one semiconductor structure is formed in each of the first and second physically separate areas. In another form, the separate regions are a bulk substrate and an electrically isolated region within the bulk substrate.

14. 发明申请

US20060030093A1 Strained semiconductor devices and method for forming at least a portion thereof 审中-公开
标题翻译：应变半导体器件及其至少一部分的形成方法
公开(公告)号：US20060030093A1
公开(公告)日：2006-02-09
申请号：US10913099
申请日：2004-08-06
申请人： Da Zhang , Brian Goolsby , Eric Luckowski , Bich-Yen Nguyen , Mariam Sadaka , Voon-Yew Thean , Ted White
发明人： Da Zhang , Brian Goolsby , Eric Luckowski , Bich-Yen Nguyen , Mariam Sadaka , Voon-Yew Thean , Ted White
IPC分类号： H01L21/8234
CPC分类号： H01L29/7842 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66651 , H01L29/66742 , H01L29/7834 , H01L29/7848 , H01L29/78687
摘要： A method for forming at least a portion of a semiconductor device includes providing a substrate and epitaxially forming an etch stop layer over the substrate. A first layer is provided over the etch stop layer, wherein the first layer is selectively etchable with regard to the etch stop layer. A structure is provided over a region of the first layer, wherein the region is not all of the first layer. In addition, the method includes etching at least a portion of the first layer that is outside of the region, wherein the etch stop layer is used an as etch stop. A strained layer is epitaxially grown in the etch-recessed region.
摘要翻译：用于形成半导体器件的至少一部分的方法包括提供衬底并在衬底上外延地形成蚀刻停止层。第一层设置在蚀刻停止层上方，其中第一层相对于蚀刻停止层可选择性地蚀刻。在第一层的区域上提供结构，其中该区域不是全部第一层。此外，该方法包括蚀刻位于该区域之外的第一层的至少一部分，其中蚀刻停止层用作蚀刻停止。在蚀刻凹陷区域中外延生长应变层。

15. 发明申请

US20070241403A1 Integrated circuit with different channel materials for P and N channel transistors and method therefor 有权
标题翻译：用于P和N沟道晶体管的不同沟道材料的集成电路及其方法
公开(公告)号：US20070241403A1
公开(公告)日：2007-10-18
申请号：US11402395
申请日：2006-04-12
申请人： Voon-Yew Thean , Bich-Yen Nguyen , Mariam Sadaka , Victor Vartanian , Ted White
发明人： Voon-Yew Thean , Bich-Yen Nguyen , Mariam Sadaka , Victor Vartanian , Ted White
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/8258 , H01L27/1203
摘要： A substrate includes a first region and a second region. The first region comprises a III-nitride layer, and the second region comprises a first semiconductor layer. A first transistor (such as an n-type transistor) is formed in and on the III-nitride layer, and a second transistor (such as a p-type transistor) is formed in and on the first semiconductor layer. The III-nitride layer may be indium nitride. In the first region, the substrate may include a second semiconductor layer, a graded transition layer over the second semiconductor layer, and a buffer layer over the transition layer, where the III-nitride layer is over the buffer layer. In the second region, the substrate may include the second semiconductor layer and an insulating layer over the second semiconductor layer, where the first semiconductor layer is over the insulating layer.
摘要翻译：衬底包括第一区域和第二区域。第一区域包括III族氮化物层，第二区域包括第一半导体层。在III族氮化物层上形成第一晶体管（例如n型晶体管），并且在第一半导体层上形成第二晶体管（例如p型晶体管）。 III族氮化物层可以是氮化铟。在第一区域中，衬底可以包括第二半导体层，在第二半导体层上的渐变过渡层，以及过渡层上的缓冲层，其中III族氮化物层在缓冲层之上。在第二区域中，衬底可以包括第二半导体层和在第二半导体层上的绝缘层，其中第一半导体层在绝缘层之上。

16. 发明申请

US20060228872A1 Method of making a semiconductor device having an arched structure strained semiconductor layer 审中-公开
标题翻译：制造具有拱形结构应变半导体层的半导体器件的方法
公开(公告)号：US20060228872A1
公开(公告)日：2006-10-12
申请号：US11093645
申请日：2005-03-30
申请人： Bich-Yen Nguyen , Shawn Thomas , Lubomir Cergel , Mariam Sadaka , Voon-Yew Thean , Peter Wennekers , Ted White , Andreas Wild , Detlev Gruetzmacher , Oliver Schmidt
发明人： Bich-Yen Nguyen , Shawn Thomas , Lubomir Cergel , Mariam Sadaka , Voon-Yew Thean , Peter Wennekers , Ted White , Andreas Wild , Detlev Gruetzmacher , Oliver Schmidt
IPC分类号： H01L21/20
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66772 , H01L29/7842 , H01L29/78648 , H01L29/78687
摘要： A method of forming a semiconductor device includes forming a local strain-inducing structure of a first semiconductor material at a point location within a dielectric layer. The local strain-inducing structure has a prescribed geometry with a surface disposed above a surface of the dielectric layer. A second semiconductor material is formed over the dielectric layer and the local strain inducing structure, wherein formation of a first portion of the second material over the dielectric layer provides a poly crystalline structure of the second material and wherein formation of a second portion of the second material over the local strain-inducing structure provides a single crystalline structure of the second material subject to mechanical strain by the surface of the local strain-inducing structure. The single crystalline structure serves as a strained semiconductor layer of the semiconductor device.
摘要翻译：形成半导体器件的方法包括在电介质层内的点位置形成第一半导体材料的局部应变诱导结构。局部应变诱导结构具有规定的几何形状，其表面设置在电介质层的表面之上。第二半导体材料形成在电介质层和局部应变诱导结构之上，其中第二材料的第一部分在电介质层上的形成提供了第二材料的多晶结构，并且其中形成第二材料的第二部分局部应变诱导结构上的材料提供由局部应变诱导结构的表面经受机械应变的第二材料的单晶结构。单晶结构用作半导体器件的应变半导体层。

17. 发明申请

US20060226492A1 Semiconductor device featuring an arched structure strained semiconductor layer 审中-公开
标题翻译：具有拱形结构的半导体器件应变半导体层
公开(公告)号：US20060226492A1
公开(公告)日：2006-10-12
申请号：US11094008
申请日：2005-03-30
申请人： Bich-Yen Nguyen , Shawn Thomas , Lubomir Cergel , Mariam Sadaka , Voon-Yew Thean , Peter Wennekers , Ted White , Andreas Wild , Detlev Gruetzmacher , Oliver Schmidt
发明人： Bich-Yen Nguyen , Shawn Thomas , Lubomir Cergel , Mariam Sadaka , Voon-Yew Thean , Peter Wennekers , Ted White , Andreas Wild , Detlev Gruetzmacher , Oliver Schmidt
IPC分类号： H01L29/94
CPC分类号： H01L29/78696 , H01L29/0649 , H01L29/42392 , H01L29/66772 , H01L29/7842 , H01L29/78648 , H01L29/78687
摘要： A semiconductor device includes a mechanically strained channel, wherein the channel comprises of a single crystalline structure of a strained semiconductor layer having a non-linear geometry, the non-linear geometry including a portion of an arch shape. The semiconductor device further includes a dielectric layer, wherein a first portion of the channel is disposed overlying a point location within the dielectric layer and a second portion of the channel is disposed overlying a portion of the dielectric layer proximate to and outside of the point location. In addition, a gate is disposed proximate to the channel for controlling current flow through the channel between first and second current handling electrodes that are coupled to the channel.
摘要翻译：半导体器件包括机械应变通道，其中通道包括具有非线性几何形状的应变半导体层的单晶结构，非线性几何形状包括拱形部分。所述半导体器件还包括介电层，其中所述沟道的第一部分设置在所述电介质层内的点位置上方，并且所述沟道的第二部分设置在所述电介质层的靠近所述点位置和外部的位置。此外，栅极靠近通道设置，用于控制电流通过耦合到通道的第一和第二电流处理电极之间的通道。

18. 发明申请

US20070272952A1 ELECTRONIC DEVICES INCLUDING A SEMICONDUCTOR LAYER 有权
标题翻译：包括半导体层的电子器件
公开(公告)号：US20070272952A1
公开(公告)日：2007-11-29
申请号：US11836844
申请日：2007-08-10
申请人： Voon-Yew Thean , Brian Goolsby , Linda McCormick , Bich-Yen Nguyen , Colita Parker , Mariam Sadaka , Victor Vartanian , Ted White , Melissa Zavala
发明人： Voon-Yew Thean , Brian Goolsby , Linda McCormick , Bich-Yen Nguyen , Colita Parker , Mariam Sadaka , Victor Vartanian , Ted White , Melissa Zavala
IPC分类号： H01L29/80
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/1203
摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
摘要翻译：电子设备可以包括第一半导体部分和第二半导体部分，其中第一半导体部分和第二半导体部分的组成彼此不同。在一个实施例中，第一和第二半导体部分可以具有彼此不同的应力。在一个实施例中，可以通过在第一半导体部分上形成氧化掩模来形成电子器件。可以在第一半导体层的第二半导体部分上形成第二半导体层，并且与第一半导体层相比具有不同的组成。可以进行氧化，并且可以增加第一半导体层的第二部分内的半导体元素（例如锗）的浓度。在另一个实施例中，可以执行选择性冷凝，并且可以在第一半导体层的第一和第二部分之间形成场隔离区。

19. 发明申请

US20070108481A1 Electronic devices including a semiconductor layer and a process for forming the same 有权
公开(公告)号：US20070108481A1
公开(公告)日：2007-05-17
申请号：US11273092
申请日：2005-11-14
申请人： Voon-Yew Thean , Brian Goolsby , Linda McCormick , Bich-Yen Nguyen , Colita Parker , Mariam Sadaka , Victor Vartanian , Ted White , Melissa Zavala
发明人： Voon-Yew Thean , Brian Goolsby , Linda McCormick , Bich-Yen Nguyen , Colita Parker , Mariam Sadaka , Victor Vartanian , Ted White , Melissa Zavala
IPC分类号： H01L29/76
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/1203
摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

20. 发明申请

US20060228842A1 Transistor fabrication using double etch/refill process 有权
标题翻译：使用双重蚀刻/补充工艺的晶体管制造
公开(公告)号：US20060228842A1
公开(公告)日：2006-10-12
申请号：US11101354
申请日：2005-04-07
申请人： Da Zhang , Jing Liu , Bich-Yen Nguyen , Voon-Yew Thean , Ted White
发明人： Da Zhang , Jing Liu , Bich-Yen Nguyen , Voon-Yew Thean , Ted White
IPC分类号： H01L21/338 , H01L21/20
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： A semiconductor fabrication process includes forming a gate electrode (120) overlying a gate dielectric (110) overlying a semiconductor substrate (102). First spacers (124) are formed on sidewalls of the gate electrode (120). First s/d trenches (130) are formed in the substrate (102) using the gate electrode (120) and first spacers (124) as a mask. The first s/d trenches (130) are filled with a first s/d structure (132). Second spacers (140) are formed on the gate electrode (120) sidewalls adjacent the first spacers (124). Second s/d trenches (150) are formed in the substrate (102) using the gate electrode (120) and the second spacers (140) as a mask. The second s/d trenches (150) are filled with a second s/d structure (152). Filling the first and second s/d trenches (130, 150) preferably includes growing the s/d structures using an epitaxial process. The s/d structures (132, 152) may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.
摘要翻译：半导体制造工艺包括形成覆盖在半导体衬底（102）上的栅电介质（110）上的栅电极（120）。第一间隔物（124）形成在栅电极（120）的侧壁上。使用栅电极（120）和第一间隔物（124）作为掩模，在基板（102）中形成第一s / d沟槽（130）。第一s / d沟槽（130）填充有第一s / d结构（132）。第二间隔物（140）形成在邻近第一间隔物（124）的栅电极（120）侧壁上。使用栅电极（120）和第二间隔物（140）作为掩模，在衬底（102）中形成第二s / d沟槽（150）。第二s / d沟槽（150）填充有第二s / d结构（152）。填充第一和第二s / d沟槽（130,150）优选地包括使用外延工艺来生长s / d结构。 s / d结构（132,152）可以是应力诱导结构，例如用于PMOS晶体管的硅锗和用于NMOS晶体管的硅碳。

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