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11. 发明授权

US08230117B2 Techniques for write-after-write ordering in a coherency managed processor system that employs a command pipeline 有权
标题翻译：在使用命令管道的一致性管理处理器系统中对写后排序进行排序的技术
公开(公告)号：US08230117B2
公开(公告)日：2012-07-24
申请号：US12420889
申请日：2009-04-09
申请人： George William Daly, Jr. , Guy Lynn Guthrie , Ross Boyd Leavens , Joseph Gerald McDonald , Michael Steven Siegel , William John Starke , Derek Edward Williams
发明人： George William Daly, Jr. , Guy Lynn Guthrie , Ross Boyd Leavens , Joseph Gerald McDonald , Michael Steven Siegel , William John Starke , Derek Edward Williams
IPC分类号： G06F3/00
CPC分类号： G06F13/4022
摘要： A technique for maintaining input/output (I/O) command ordering on a bus includes assigning a channel identifier to I/O commands of an I/O stream. In this case, the channel identifier indicates the I/O commands belong to the I/O stream. A command location indicator is assigned to each of the I/O commands. The command location indicator provides an indication of which one of the I/O commands is a start command in the I/O stream and which of the I/O commands are continue commands in the I/O stream. The I/O commands are issued in a desired completion order. When a first one of the I/O commands does not complete successfully, the I/O commands in the I/O stream are reissued on the bus starting at the first one of the I/O commands that did not complete successfully.
摘要翻译：用于在总线上维持输入/输出（I / O）命令排序的技术包括将信道标识符分配给I / O流的I / O命令。在这种情况下，通道标识符表示属于I / O流的I / O命令。命令位置指示符分配给每个I / O命令。命令位置指示器提供I / O命令中的哪一个是I / O流中的起始命令以及I / O命令中的哪一个在I / O流中继续命令的指示。 I / O命令以所需的完成顺序发出。当第一个I / O命令未成功完成时，I / O流中的I / O命令将从未成功完成的第一个I / O命令开始在总线上重新发出。

12. 发明授权

US08006244B2 Controller for multiple instruction thread processors 失效
标题翻译：多指令线程处理器的控制器
公开(公告)号：US08006244B2
公开(公告)日：2011-08-23
申请号：US10915983
申请日：2004-08-11
申请人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Fabrice Jean Verplanken
发明人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Fabrice Jean Verplanken
IPC分类号： G06F9/46
CPC分类号： G06F9/3802 , G06F9/3851
摘要： A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.
摘要翻译：机制控制多线程处理器，使得当第一线程遇到第一预定义时间间隔的等待时间事件时，临时控制在第一预定义时间间隔的持续时间内被传送到备用执行线程，然后返回到原始线程。当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。

13. 发明授权

US06769033B1 Network processor processing complex and methods 失效
标题翻译：网络处理器处理复杂和方法
公开(公告)号：US06769033B1
公开(公告)日：2004-07-27
申请号：US09384691
申请日：1999-08-27
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Piyush Chunilal Patel , Mark Anthony Rinaldi , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Piyush Chunilal Patel , Mark Anthony Rinaldi , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F900
CPC分类号： H04L49/602 , G06F15/80 , H04L49/351
摘要： A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of an embedded processor complex with a suite of peripherals, all formed on a common semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate, while storage of transiting data flow portions is provided by memory peripherals and interfaces to external memory elements.
摘要翻译：可用于网络交换设备的网络处理器和操作这样的处理器的方法，其中通过嵌入式处理器复合体与一组外围设备的协作来增强数据流处理和灵活性，这些外围设备都形成在公共半导体衬底上。接口处理器提供用于入站和出站数据流的数据路径，并且在存储在形成于半导体衬底上的指令存储器中的指令的控制下操作，同时由存储器外围设备和与外部存储器元件的接口提供过渡数据流部分的存储。

14. 发明授权

US06588008B1 Assembler tool for processor-coprocessor computer systems 失效
标题翻译：处理器 - 协处理器计算机系统的汇编工具
公开(公告)号：US06588008B1
公开(公告)日：2003-07-01
申请号：US09546755
申请日：2000-04-11
申请人： Marco C. Heddes , Ross Boyd Leavens , Mark Anthony Rinaldi
发明人： Marco C. Heddes , Ross Boyd Leavens , Mark Anthony Rinaldi
IPC分类号： G06F945
CPC分类号： G06F9/30043 , G06F8/47 , G06F9/30101 , G06F9/30145 , G06F9/30167 , G06F9/3885
摘要： A central processor-coprocessor assembly comprising an assembler software tool for extending the base central processor tasks into at least one coprocessor. What is important is that the assembler software tool does not need to be rebuilt when changes are made to the coprocessor elements. The invention allows assembly time extension of a base core language processing (CLP) programming model, without the need to rebuild the assembler tool itself. The assembler tool comprises a set of commands which enable the central processor to manipulate the coprocessor registers, and a coprocessor execute instruction, which initiates command processing on the coprocessor. The present invention simplifies the maintenance of the assembler tool through multiple hardware revisions by enabling hardware designers to update their coprocessor definition files to reflect new or modified coprocessors.
摘要翻译：一种中央处理器 - 协处理器组件，其包括用于将基本中央处理器任务扩展到至少一个协处理器的汇编器软件工具。重要的是，当对协处理器元素进行更改时，汇编程序软件工具不需要重新构建。本发明允许基本核心语言处理（CLP）编程模型的组装时间扩展，而不需要重建汇编器工具本身。汇编器工具包括使得中央处理器能够操纵协处理器寄存器的一组命令，以及协处理器执行指令，其在协处理器上启动命令处理。本发明通过使得硬件设计者能够更新其协处理器定义文件以反映新的或修改的协处理器，通过多个硬件修订来简化了汇编工具的维护。

15. 发明申请

US20130152099A1 DYNAMICALLY CONFIGURABLE HARDWARE QUEUES FOR DISPATCHING JOBS TO A PLURALITY OF HARDWARE ACCELERATION ENGINES 有权
公开(公告)号：US20130152099A1
公开(公告)日：2013-06-13
申请号：US13323914
申请日：2011-12-13
申请人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, JR. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
发明人： Brian Mitchell Bass , Bartholomew Blaner , George William Daly, JR. , Jeffrey Haskell Derby , Ross Boyd Leavens , Joseph Gerald McDonald
IPC分类号： G06F9/50
CPC分类号： G06F9/5038 , G06F9/4843 , G06F9/5027 , G06F2209/5021
摘要： A computer system having a plurality of processing resources, including a sub-system for scheduling and dispatching processing jobs to a plurality of hardware accelerators, the subsystem further comprising a job requestor, for requesting jobs having bounded and varying latencies to be executed on the hardware accelerators; a queue controller to manage processing job requests directed to a plurality of hardware accelerators; and multiple hardware queues for dispatching jobs to the plurality of hardware acceleration engines, each queue having a dedicated head of queue entry, dynamically sharing a pool of queue entries, having configurable queue depth limits, and means for removing one or more jobs across all queues.

16. 发明申请

US20100262720A1 TECHNIQUES FOR WRITE-AFTER-WRITE ORDERING IN A COHERENCY MANAGED PROCESSOR SYSTEM THAT EMPLOYS A COMMAND PIPELINE 有权
标题翻译：在使用命令管道的协调管理处理器系统中进行写后写入的技术
公开(公告)号：US20100262720A1
公开(公告)日：2010-10-14
申请号：US12420889
申请日：2009-04-09
申请人： George William Daly, JR. , Guy Lynn Guthrie , Ross Boyd Leavens , Joseph Gerald McDonald , Michael Steven Siegel , William John Starke , Derek Edward Williams
发明人： George William Daly, JR. , Guy Lynn Guthrie , Ross Boyd Leavens , Joseph Gerald McDonald , Michael Steven Siegel , William John Starke , Derek Edward Williams
IPC分类号： G06F3/00
CPC分类号： G06F13/4022
摘要： A technique for maintaining input/output (I/O) command ordering on a bus includes assigning a channel identifier to I/O commands of an I/O stream. In this case, the channel identifier indicates the I/O commands belong to the I/O stream. A command location indicator is assigned to each of the I/O commands. The command location indicator provides an indication of which one of the I/O commands is a start command in the I/O stream and which of the I/O commands are continue commands in the I/O stream. The I/O commands are issued in a desired completion order. When a first one of the I/O commands does not complete successfully, the I/O commands in the I/O stream are reissued on the bus starting at the first one of the I/O commands that did not complete successfully.
摘要翻译：用于在总线上维持输入/输出（I / O）命令排序的技术包括将信道标识符分配给I / O流的I / O命令。在这种情况下，通道标识符表示属于I / O流的I / O命令。命令位置指示符分配给每个I / O命令。命令位置指示器提供I / O命令中的哪一个是I / O流中的起始命令以及I / O命令中的哪一个在I / O流中继续命令的指示。 I / O命令以所需的完成顺序发出。当第一个I / O命令未成功完成时，I / O流中的I / O命令将从未成功完成的第一个I / O命令开始在总线上重新发出。

17. 发明授权

US07093109B1 Network processor which makes thread execution control decisions based on latency event lengths 失效
标题翻译：基于延迟事件长度的线程执行控制决策的网络处理器
公开(公告)号：US07093109B1
公开(公告)日：2006-08-15
申请号：US09542189
申请日：2000-04-04
申请人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Fabrice Jean Verplanken
发明人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Fabrice Jean Verplanken
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3802
摘要： A control mechanism is established between a network processor and a tree search coprocessor to deal with latencies in accessing the data such as information formatted in a tree structure. A plurality of independent instruction execution threads are queued to enable them to have rapid access to the shared memory. If execution of a thread becomes stalled due to a latency event, full control is granted to the next thread in the queue. The grant of control is temporary when a short latency event occurs or full when a long latency event occurs. Control is returned to the original thread when a short latency event is completed. Each execution thread utilizes an instruction prefetch buffer that collects instructions for idle execution threads when the instruction bandwidth is not fully utilized by an active execution thread. The thread execution control is governed by the collective functioning of a FIFO, an arbiter and a thread control state machine.
摘要翻译：在网络处理器和树形搜索协处理器之间建立一种控制机制来处理访问诸如以树结构格式化的信息的数据的延迟。排队多个独立的指令执行线程使其能够快速访问共享存储器。如果由于延迟事件导致线程执行失败，则会对队列中的下一个线程授予完全控制权。当长时间延迟事件发生时，发生短延迟事件或满时，授权控制是暂时的。当短暂延迟事件完成时，控制返回到原始线程。每个执行线程使用指令预取缓冲器，当指令带宽未被活动执行线程充分利用时，该指令预取缓冲器收集空闲执行线程的指令。线程执行控制由FIFO，仲裁器和线程控制状态机的集合功能决定。

18. 发明授权

US06931641B1 Controller for multiple instruction thread processors 失效
标题翻译：多指令线程处理器的控制器
公开(公告)号：US06931641B1
公开(公告)日：2005-08-16
申请号：US09542206
申请日：2000-04-04
申请人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Fabrice Jean Verplanken
发明人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Fabrice Jean Verplanken
IPC分类号： G06F9/46 , G06F9/38 , G06F9/48 , G06F9/52 , G06F15/16 , G06F9/00
CPC分类号： G06F9/3802 , G06F9/3851
摘要： A mechanism controls a multi-thread processor so that when a fist thread encounters a latency event to a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.
摘要翻译：机构控制多线程处理器，使得当第一线程遇到延迟事件到第一预定义时间间隔时，临时控制在第一预定义时间间隔的持续时间内传送到备用执行线程，然后返回到原始线程。当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。

19. 发明授权

US06785278B1 Methods, systems and computer program products for hashing address values 失效
标题翻译：用于散列地址值的方法，系统和计算机程序产品
公开(公告)号：US06785278B1
公开(公告)日：2004-08-31
申请号：US09210222
申请日：1998-12-10
申请人： Jean Louis Calvignac , Marco C. Heddes , Clark Debs Jeffries , Ross Boyd Leavens , Gerald Arnold Marin , Piyush Chunilal Patel , Atef Omar Zaghloul
发明人： Jean Louis Calvignac , Marco C. Heddes , Clark Debs Jeffries , Ross Boyd Leavens , Gerald Arnold Marin , Piyush Chunilal Patel , Atef Omar Zaghloul
IPC分类号： H04L1228
CPC分类号： H04L12/4625 , H04L45/745
摘要： Methods systems and computer program products are provided for hashing address values that exhibit banding in a plurality of regions of an address space defined by at least two segments of the address values, by performing at least one of a translation and a rotation of the at least two segments to thereby map the at least two segments from the plurality of regions to one of the plurality of regions.
摘要翻译：提供了方法系统和计算机程序产品，用于通过执行至少一个地址值的平移和旋转中的至少一个来散列地址值，所述地址值在由地址值的至少两个段定义的地址空间的多个区域中呈现带状从而将多个区域中的至少两个区段映射到多个区域中的一个区域。

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