专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07945833B1 Method and apparatus for pipelined scan compression 有权
标题翻译：流水线扫描压缩方法和装置
公开(公告)号：US07945833B1
公开(公告)日：2011-05-17
申请号：US11889710
申请日：2007-08-15
申请人： Laung-Terng (L.-T.) Wang , Nur A. Touba , Boryau (Jack) Sheu , Shianling Wu , Zhigang Jiang
发明人： Laung-Terng (L.-T.) Wang , Nur A. Touba , Boryau (Jack) Sheu , Shianling Wu , Zhigang Jiang
IPC分类号： G01R31/3177 , G01R31/40
CPC分类号： G01R31/318547
摘要： A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step.
摘要翻译：一种用于在基于扫描的集成电路中减少测试数据量和测试应用时间的流水线扫描压缩方法和装置，而不降低扫描测试模式或自检模式下扫描链操作的速度。基于扫描的集成电路包含一个或多个扫描链，每个扫描链包括串联耦合的一个或多个扫描单元。该方法和装置包括一个解压缩器，它包括一个或多个移位寄存器，组合逻辑网络和可选的扫描连接器。解压缩器在其压缩的扫描输入端解压缩压缩的扫描图案，并将解压缩器的输出端上产生的解压缩扫描图案驱动到基于扫描的集成电路的扫描数据输入端。由所述组合逻辑网络施加的任何输入约束被并入自动测试模式生成（ATPG）程序中，用于一步地生成针对一个或多个选定故障的压缩扫描模式。

12. 发明授权

US08949299B2 Method and apparatus for hybrid ring generator design 有权
标题翻译：混合环形发电机设计方法与装置
公开(公告)号：US08949299B2
公开(公告)日：2015-02-03
申请号：US13195524
申请日：2011-08-01
申请人： Laung-Terng Wang , Nur A. Touba
发明人： Laung-Terng Wang , Nur A. Touba
IPC分类号： G06F7/58
CPC分类号： G06F7/584 , G06F2207/583
摘要： A method and apparatus for generating a pseudorandom sequence using a hybrid ring generator with low hardware cost. When a primitive polynomial over GF(2) is selected as the characteristic polynomial f(x) to construct a hybrid ring generator, the circuit implementing f(x) will generate a maximum-length sequence (m-sequence). The hybrid ring generator offers unmatched benefits over existing linear feedback shift register (LFSR) based maximum-length sequence generators (MLSGs). Assume k 2-input XOR gates are required in a standard or modular LFSR design. These benefits include requiring only (k+1)/2 2-input XOR gates, having at most one level of a 2-input XOR gate between any pair of flip-flops, enabling the output of each flip-flop to drive at most 2 fanout nodes, and creating a highly regular structure that makes the new design more layout and timing friendly.
摘要翻译：一种使用低硬件成本的混合环形发生器产生伪随机序列的方法和装置。当选择GF（2）上的原始多项式作为特征多项式f（x）构建混合环形发生器时，实现f（x）的电路将产生最大长度序列（m序列）。混合环形发生器与现有的基于最大长度序列发生器（MLSG）的线性反馈移位寄存器（LFSR）相比具有无与伦比的优势。假设在标准或模块化LFSR设计中需要k个2输入XOR门。这些优点包括仅需要（k + 1）/ 2个2输入异或门，在任何一对触发器之间具有至多一个2输入异或门电平，使每个触发器的输出最多驱动 2个扇出节点，并创建一个高度规则的结构，使新的设计更加布局和时间友好。

13. 发明申请

US20130036146A1 METHOD AND APPARATUS FOR HYBRID RING GENERATOR DESIGN 有权
标题翻译：混合发电机设计方法与装置
公开(公告)号：US20130036146A1
公开(公告)日：2013-02-07
申请号：US13195524
申请日：2011-08-01
申请人： Laung-Terng Wang , Nur A. Touba
发明人： Laung-Terng Wang , Nur A. Touba
IPC分类号： G06F7/58
CPC分类号： G06F7/584 , G06F2207/583
摘要： A method and apparatus for generating a pseudorandom sequence using a hybrid ring generator with low hardware cost. When a primitive polynomial over GF(2) is selected as the characteristic polynomial f(x) to construct a hybrid ring generator, the circuit implementing f(x) will generate a maximum-length sequence (m-sequence). The hybrid ring generator offers unmatched benefits over existing linear feedback shift register (LFSR) based maximum-length sequence generators (MLSGs). Assume k 2-input XOR gates are required in a standard or modular LFSR design. These benefits include requiring only (k+1)/2 2-input XOR gates, having at most one level of a 2-input XOR gate between any pair of flip-flops, enabling the output of each flip-flop to drive at most 2 fanout nodes, and creating a highly regular structure that makes the new design more layout and timing friendly.
摘要翻译：一种使用低硬件成本的混合环形发生器产生伪随机序列的方法和装置。当选择GF（2）上的原始多项式作为特征多项式f（x）构建混合环形发生器时，实现f（x）的电路将产生最大长度序列（m序列）。混合环形发生器与现有的基于最大长度序列发生器（MLSG）的线性反馈移位寄存器（LFSR）相比具有无与伦比的优势。假设在标准或模块化LFSR设计中需要k个2输入XOR门。这些优点包括仅需要（k + 1）/ 2个2输入异或门，在任何一对触发器之间具有至多一个2输入异或门电平，使每个触发器的输出最多驱动 2个扇出节点，并创建一个高度规则的结构，使新的设计更加布局和时间友好。

14. 发明授权

US6061818A Altering bit sequences to contain predetermined patterns 失效
标题翻译：改变位序列以包含预定模式
公开(公告)号：US6061818A
公开(公告)日：2000-05-09
申请号：US074848
申请日：1998-05-08
申请人： Nur A. Touba , Edward J. McCluskey
发明人： Nur A. Touba , Edward J. McCluskey
IPC分类号： G01R31/3185 , G01R31/28 , G06F11/00
CPC分类号： G01R31/318385 , G01R31/318547
摘要： A low-overhead scheme for built-in self-test of digital designs incorporating scan allows for complete (100%) fault coverage without modifying the function logic and without degrading system performance (beyond using scan). By altering a pseudo-random bit sequence with bit-fixing logic at an LFSR's serial output, deterministic test cubes that detect random pattern-resistant faults are generated. A procedure for synthesizing the bit-fixing logic allows for complete fault coverage with low hardware overhead. Also, the present approach permits the use of small LFSR's for generating the pseudo-random bit sequence. The faults that are not detected because of linear dependencies in the LFSR can be detected by generating more deterministic cubes at the expense of additional bit-fixing logic.
摘要翻译：内置扫描数字设计的内置自检的低开销方案允许完全（100％）的故障覆盖，而无需修改功能逻辑，而不降低系统性能（超出使用扫描）。通过在LFSR的串行输出端改变带有位固定逻辑的伪随机位序列，生成检测随机模式抗故障的确定性测试立方体。用于合成位固定逻辑的过程允许以低硬件开销完成故障覆盖。此外，本方法允许使用小的LFSR来生成伪随机比特序列。由于LFSR中的线性相关性而未检测到的故障可以通过以额外的位固定逻辑为代价产生更多的确定性立方体来检测。

15. 发明授权

US07925947B1 X-canceling multiple-input signature register (MISR) for compacting output responses with unknowns 有权
标题翻译： X取消多输入签名寄存器（MISR），用于压缩具有未知数的输出响应
公开(公告)号：US07925947B1
公开(公告)日：2011-04-12
申请号：US12007693
申请日：2008-01-14
申请人： Nur A. Touba , Laung-Terng (L.-T.) Wang
发明人： Nur A. Touba , Laung-Terng (L.-T.) Wang
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A method and apparatus for compacting test responses containing unknown (X) values in a scan-based integrated circuit using an X-canceling multiple-input signature register (MISR) to produce a known (non-X) signature. The known (non-X) signature is obtained by selectively exclusive-ORing (XORing) together combinations of MISR bits which are linearly dependent in terms of the unknown (X) values using a selective XOR network.
摘要翻译：一种使用X取消多输入签名寄存器（MISR）在基于扫描的集成电路中压缩包含未知（X）值的测试响应以产生已知（非X）签名的方法和装置。通过使用选择性XOR网络将与在未知（X）值方面线性相关的MISR位的组合一起选择性地异或（异或）获得已知（非X）签名。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式