专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20080135912A1 Memory device and method of fabricating the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20080135912A1
公开(公告)日：2008-06-12
申请号：US11976389
申请日：2007-10-24
申请人： Chang-Hyun Lee , Jung-dal Choi
发明人： Chang-Hyun Lee , Jung-dal Choi
IPC分类号： H01L29/788 , H01L21/8247
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.
摘要翻译：一种非易失性存储器，包括串联的多个存储晶体管，其中在其间的源极/漏极和沟道区域是第一类型和选择晶体管，在多个存储晶体管的每个端部串联，其中每个选择的沟道区域晶体管是第一类型。第一种类型可以是n型或p型。非易失性存储器还可以包括串联在选择晶体管之一和串联的多个存储晶体管之间的多个存储晶体管的一端的第一虚拟选择晶体管，以及多个存储晶体管的另一端的第二虚拟选择晶体管串联在另一个选择晶体管和多个存储晶体管之间的存储晶体管。

12. 发明申请

US20060022276A1 Methods of forming semiconductor devices including a resistor in a resistor region and devices so formed 审中-公开
标题翻译：在电阻器区域中形成包括电阻器的半导体器件的形成方法和如此形成的器件
公开(公告)号：US20060022276A1
公开(公告)日：2006-02-02
申请号：US11023892
申请日：2004-12-28
申请人： Jin-taek Park , Jung-dal Choi , Sung-hoi Hur , Joon-hee Lee
发明人： Jin-taek Park , Jung-dal Choi , Sung-hoi Hur , Joon-hee Lee
IPC分类号： H01L29/94
CPC分类号： H01L27/11526 , H01L27/0629 , H01L27/105 , H01L27/115 , H01L27/11529 , H01L27/11531 , H01L28/20
摘要： Methods of forming a semiconductor device can include forming a first conductive layer of a gate electrode on a substrate of a device and forming a second conductive layer of a resistor, that is different than the first conductive layer, on the substrate spaced-apart from the gate electrode. Related devices are also disclosed.
摘要翻译：形成半导体器件的方法可以包括在器件的衬底上形成栅电极的第一导电层，并且在与第一导电层隔开的衬底上形成与第一导电层不同的电阻器的第二导电层栅电极。还公开了相关设备。

13. 发明授权

US08765572B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08765572B2
公开(公告)日：2014-07-01
申请号：US13168312
申请日：2011-06-24
申请人： Yong-lack Choi , Chang-hyun Cho , Seung-pil Chung , Hyun-seok Jang , Du-heon Song , Jung-dal Choi
发明人： Yong-lack Choi , Chang-hyun Cho , Seung-pil Chung , Hyun-seok Jang , Du-heon Song , Jung-dal Choi
IPC分类号： H01L21/764
CPC分类号： H01L21/7682 , H01L27/11521 , H01L27/11526
摘要： A method of fabricating a semiconductor device, in which an interference effect between word lines is substantially reduced or eliminated, includes forming a plurality of gate patterns on a substrate; forming a first insulating layer between the gate patterns, the first insulating layer filling a region between the gate patterns; etching the first insulating layer to remove a portion of the first insulating layer to a predetermined depth; and forming a second insulating layer on the gate patterns and the first insulating layer. A low-dielectric-constant material is formed between the gate patterns.
摘要翻译：一种制造半导体器件的方法，其中字线之间的干涉效应被显着地减少或消除，包括在衬底上形成多个栅极图案; 在所述栅极图案之间形成第一绝缘层，所述第一绝缘层填充所述栅极图案之间的区域; 蚀刻第一绝缘层以将第一绝缘层的一部分去除到预定深度; 以及在栅极图案和第一绝缘层上形成第二绝缘层。在栅极图案之间形成低介电常数材料。

14. 发明申请

US20110260237A1 VERTICAL MEMORY DEVICES WITH QUANTUM-DOT CHARGE STORAGE CELLS 有权
标题翻译：具有量子充电储存电池的垂直存储器件
公开(公告)号：US20110260237A1
公开(公告)日：2011-10-27
申请号：US13042051
申请日：2011-03-07
申请人： Jae-goo Lee , Jung-dal Choi , Young-woo Park
发明人： Jae-goo Lee , Jung-dal Choi , Young-woo Park
IPC分类号： H01L29/792 , H01L29/78
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L29/42332 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： A memory device includes a substrate, a semiconductor column extending perpendicularly from the substrate and a plurality of spaced-apart charge storage cells disposed along a sidewall of the semiconductor column. Each of the storage cells includes a tunneling insulating layer disposed on the sidewall of the semiconductor column, a polymer layer disposed on the tunneling insulating layer, a plurality of quantum dots disposed on or in the polymer layer and a blocking insulating layer disposed on the polymer layer.
摘要翻译：存储器件包括衬底，从衬底垂直延伸的半导体柱和沿着半导体柱的侧壁设置的多个间隔开的电荷存储单元。每个存储单元包括设置在半导体柱的侧壁上的隧道绝缘层，设置在隧道绝缘层上的聚合物层，设置在聚合物层上或其中的多个量子点以及设置在聚合物上的阻挡绝缘层层。

15. 发明授权

US07808036B2 Memory device and method of fabricating the same 有权
公开(公告)号：US07808036B2
公开(公告)日：2010-10-05
申请号：US11976389
申请日：2007-10-24
申请人： Chang-Hyun Lee , Jung-dal Choi
发明人： Chang-Hyun Lee , Jung-dal Choi
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.

16. 发明申请

US20090321815A1 Non-volatile memory device and method of fabricating the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20090321815A1
公开(公告)日：2009-12-31
申请号：US12453035
申请日：2009-04-28
申请人： Suk-kang Sung , Jung-dal Choi , Choong-ho Lee , Sung-hoi Hur
发明人： Suk-kang Sung , Jung-dal Choi , Choong-ho Lee , Sung-hoi Hur
IPC分类号： H01L29/792 , H01L27/092
CPC分类号： H01L21/823493 , H01L21/823456 , H01L27/11568 , H01L27/11573 , H01L29/792
摘要： A non-volatile memory device, including a substrate of a first conductivity type, the substrate including a plurality of wells of a second conductivity type, a plurality of memory cells in one of the plurality of wells of the second conductivity type, and a peripheral circuit including at least one first transistor of the second conductivity type on the substrate, and at least one second transistor of the first conductivity type in another one of the plurality of wells of the second conductivity type.
摘要翻译：一种非易失性存储器件，包括第一导电类型的衬底，所述衬底包括多个第二导电类型的阱，多个第二导电类型的阱之一中的多个存储单元，以及周边包括至少一个第一导电类型的第一晶体管和第二导电类型的另一个第二导电类型的第二导体类型的第二晶体管。

17. 发明授权

US5734609A Integrated circuit memory devices having reduced susceptibility to inadvertent programming and erasure and methods of operating same 失效
标题翻译：具有降低对无意编程和擦除的敏感性的集成电路存储器件及其操作方法
公开(公告)号：US5734609A
公开(公告)日：1998-03-31
申请号：US757266
申请日：1996-11-29
申请人： Jung-dal Choi , Dong-Jun Kim
发明人： Jung-dal Choi , Dong-Jun Kim
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： G11C16/0483
摘要： Integrated circuit memory devices having reduced susceptibility to inadvertent programming and erasure include an array of memory cells arranged as a plurality of NAND strings of EEPROM cells which share common control lines (e.g., SSL1, SSL2) and word lines (e.g., WL1-WLn). These NAND strings preferably comprise a linear array or chain of EEPROM cells having first and second ends and first and second select transistors (ST1, ST2) coupled (directly or indirectly) to (he first and second ends, respectively. To provide improved program and erase capability, a pair of NAND strings are provided in antiparallel and share a common bit line. However, the pair of NAND strings are formed in respective nonoverlapping well regions in a substrate so that the channel regions of the EEPROM cells in respective NAND strings can be individually controlled (e.g., raised) to prevent inadvertent programming or erasing when cells in adjacent strings are being programmed or erased, respectively.
摘要翻译：具有降低的对无意编程和擦除的敏感性的集成电路存储器件包括布置成共享共同控制线（例如，SSL1，SSL2）和字线（例如，WL1-WLn）的多个EEPROM单元的NAND串的存储器单元的阵列，。这些NAND串优选地包括具有第一和第二端的线性阵列或EEPROM单元串，以及分别连接（直接或间接）到其第一和第二端的第一和第二选择晶体管（ST1，ST2），以提供改进的程序和擦除能力，反并联提供一对NAND串并共享一个公共位线，但是这对NAND串形成在衬底中的各个非重叠阱区中，使得各个NAND串中的EEPROM单元的沟道区可以分别控制（例如，升高）以防止在相邻串中的单元被编程或擦除时意外编程或擦除。

18. 发明授权

US08334562B2 Memory device and method of fabricating the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US08334562B2
公开(公告)日：2012-12-18
申请号：US12805962
申请日：2010-08-26
申请人： Chang-Hyun Lee , Jung-dal Choi
发明人： Chang-Hyun Lee , Jung-dal Choi
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series.
摘要翻译：一种非易失性存储器，包括串联的多个存储晶体管，其中，它们之间的源极/漏极和沟道区域是第一类型和选择晶体管，在多个存储晶体管的每个端部串联，其中每个选择的沟道区域晶体管是第一类型。第一种类型可以是n型或p型。非易失性存储器还可以包括串联在选择晶体管之一和串联的多个存储晶体管之间的多个存储晶体管的一端的第一虚拟选择晶体管，以及多个存储晶体管的另一端的第二虚拟选择晶体管串联在另一个选择晶体管和多个存储晶体管之间的存储晶体管。

19. 发明申请

US20110233610A1 Nonvolatile Memory Devices Having Memory Cell Transistors Therein with Lower Bandgap Source/Drain Regions 有权
标题翻译：具有存储单元晶体管的非易失性存储器件具有较低的带隙源/漏区
公开(公告)号：US20110233610A1
公开(公告)日：2011-09-29
申请号：US12974542
申请日：2010-12-21
申请人： Byung-kyu Cho , Kwang-soo Seol , Sung-hoi Hur , Jung-dal Choi
发明人： Byung-kyu Cho , Kwang-soo Seol , Sung-hoi Hur , Jung-dal Choi
IPC分类号： H01L29/772
CPC分类号： H01L27/11521 , H01L27/11524
摘要： Nonvolatile memory devices include a plurality of nonvolatile memory cell transistors having respective channel regions within a semiconductor layer formed of a first semiconductor material and respective source/drain regions formed of a second semiconductor material, which has a smaller bandgap relative to the first semiconductor material. The source/drain regions can form non-rectifying junctions with the channel regions. The source/drain regions may include germanium (e.g., Ge or SiGe regions), the semiconductor layer may be a P-type silicon layer and the source/drain regions of the plurality of nonvolatile memory cell transistors may be P-type germanium or P-type silicon germanium.
摘要翻译：非易失性存储器件包括多个非易失性存储单元晶体管，其在由第一半导体材料形成的半导体层内的相应沟道区和由第二半导体材料形成的相应的源极/漏极区相互相对于第一半导体材料具有较小的带隙。源极/漏极区域可以与沟道区域形成非整流结。源极/漏极区域可以包括锗（例如Ge或SiGe区域），半导体层可以是P型硅层，并且多个非易失性存储单元晶体管的源极/漏极区域可以是P型锗或P 型硅锗。

20. 发明授权

US08018781B2 Method of operating nonvolatile memory device 有权
标题翻译：操作非易失性存储器件的方法
公开(公告)号：US08018781B2
公开(公告)日：2011-09-13
申请号：US12071960
申请日：2008-02-28
申请人： Kwang-soo Seol , Sang-jin Park , Sung-hoon Lee , Sung-il Park , Jong-seob Kim , Jung-dal Choi , Ki-hwan Choi , Jae-sung Sim , Seung-hyun Moon
发明人： Kwang-soo Seol , Sang-jin Park , Sung-hoon Lee , Sung-il Park , Jong-seob Kim , Jung-dal Choi , Ki-hwan Choi , Jae-sung Sim , Seung-hyun Moon
IPC分类号： G11C11/34
CPC分类号： G11C16/14
摘要： Provided is a method of operating a nonvolatile memory device to perform an erase operation. The method includes applying a composite pulse including a direct current (DC) pulse and a DC perturbation pulse to the nonvolatile memory device to perform the erase operation.
摘要翻译：提供了一种操作非易失性存储器件以执行擦除操作的方法。该方法包括将包括直流（DC）脉冲和DC扰动脉冲的复合脉冲施加到非易失性存储器件以执行擦除操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式