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11. 发明授权

US5422295A Method for forming a semiconductor memory device having a vertical multi-layered storage electrode 失效
标题翻译：用于形成具有垂直多层存储电极的半导体存储器件的方法
公开(公告)号：US5422295A
公开(公告)日：1995-06-06
申请号：US164671
申请日：1993-12-10
申请人： Young-jae Choi , Tae-young Chung , Jong-woo Park , Young-pil Kim
发明人： Young-jae Choi , Tae-young Chung , Jong-woo Park , Young-pil Kim
IPC分类号： H01L27/04 , H01L21/02 , H01L21/265 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L28/86 , H01L21/26533 , H01L28/87 , H01L28/88
摘要： A manufacturing method for a semiconductor memory device including a capacitor having a double fin-shaped structure is provided, wherein a storage electrode is formed by applying a thick planar material capable of being wet-etched between the double fins consisting of conductive layers. The storage electrode is formed by forming a thin, high temperature oxide film having an etching rate which is great. Thus, the resulting memory cell's topography is improved and damage to the storage electrode is decreased.
摘要翻译：提供了一种包括具有双鳍状结构的电容器的半导体存储器件的制造方法，其中通过在由导电层组成的双翅片之间施加能够被湿蚀刻的厚平面材料形成存储电极。存储电极通过形成蚀刻速率大的薄的高温氧化膜形成。因此，所得到的存储单元的形貌得到改善，并且对存储电极的损坏降低。

12. 发明申请

US20100208381A1 Magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices 失效
标题翻译：磁性分组存储器存储设备，包括这种设备的存储器系统以及控制这些设备的方法
公开(公告)号：US20100208381A1
公开(公告)日：2010-08-19
申请号：US12658807
申请日：2010-02-16
申请人： Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Jong-wan Kim , Hyun-ho Choi , Young-pil Kim , Sung-chul Lee
发明人： Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Jong-wan Kim , Hyun-ho Choi , Young-pil Kim , Sung-chul Lee
IPC分类号： G11B19/02
CPC分类号： G11C11/15 , G11C5/04
摘要： A memory device is comprised of a magnetic structure that stores information in a plurality of domains of the magnetic structure. A write unit writes information to at least one of the plurality of domains of the magnetic structure by applying a write current to the magnetic structure in response to a control signal. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure in response to the control signal. A domain wall movement control unit is coupled to a portion of the magnetic structure and moves information stored in the plurality of domains in the magnetic structure to other domains in the magnetic structure in response to the control signal. The write unit, the read unit and the domain wall movement control unit are all coupled to the same control signal line that provides the control signal.
摘要翻译：存储器件由将磁信息存储在磁结构的多个域中的磁结构构成。写单元响应于控制信号向磁结构施加写入电流，将信息写入磁结构的多个域中的至少一个。读取单元通过响应于控制信号向磁性结构施加读取电流，从磁性结构的多个域中的至少一个域读取信息。畴壁移动控制单元耦合到磁结构的一部分，并且响应于控制信号将存储在磁结构中的多个域中的信息移动到磁结构中的其他区域。写单元，读单元和域壁移动控制单元都耦合到提供控制信号的相同控制信号线。

13. 发明申请

US20090122593A1 Write driver circuit for phase-change memory, memory including the same, and associated methods 有权
标题翻译：为相变存储器写入驱动电路，包含相同的存储器及相关方法
公开(公告)号：US20090122593A1
公开(公告)日：2009-05-14
申请号：US12292200
申请日：2008-11-13
申请人： Beak-hyung Cho , Kwang-ho Kim , Young-pil Kim
发明人： Beak-hyung Cho , Kwang-ho Kim , Young-pil Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0038 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/0069 , G11C2013/0078
摘要： A write driver circuit for a memory that includes phase-change memory cells changeable between a RESET state resistance and a SET state resistance in response to an applied current pulse, the write driver circuit including a write current level adjusting unit configured to determine first to n-th SET state current levels in response to a SET state current level signal, where n is an integer greater than 1, and configured to determine a RESET state current level in response to a RESET state current level signal, and a write current output unit configured to generate one of a SET state current pulse and a RESET state current pulse corresponding to a SET state current level or a RESET state current level determined by the write current level adjusting unit.
摘要翻译：一种用于存储器的写入驱动器电路，其包括响应于所施加的电流脉冲而在RESET状态电阻和SET状态电阻之间改变的相变存储器单元，所述写入驱动器电路包括写入电平电平调整单元，其被配置为从第一至第n 响应于SET状态电流电平信号，其中n是大于1的整数，并且被配置为响应于RESET状态电流信号确定RESET状态电流电平，并且写入电流输出单元被配置为产生与由写入电平电平调整单元确定的SET状态电流电平或RESET状态电流电平对应的SET状态电流脉冲和RESET状态电流脉冲之一。

14. 发明授权

US07060575B2 Semiconductor device having transistor and method of manufacturing the same 有权
公开(公告)号：US07060575B2
公开(公告)日：2006-06-13
申请号：US10426585
申请日：2003-04-30
申请人： Beom-jun Jin , Byeong-yun Nam , Young-pil Kim
发明人： Beom-jun Jin , Byeong-yun Nam , Young-pil Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/76897 , H01L21/823475 , H01L29/6653 , Y10S257/90
摘要： A method of forming self-aligned contact holes exposing source/drain regions in a semiconductor substrate using only etch mask layers is provided. In the method, sacrificial spacers are formed of a material having an excellent etching selectivity to the etch mask layers at sidewalls of gate electrodes in a cell area. Also, an interlevel dielectric layer is formed of a material having an excellent etching selectivity to the etch mask layers. The sacrificial spacers are removed when forming the self-aligned contact holes. Dielectric spacers are formed of a material having a low dielectric constant, without considering its etching selectivity to the interlevel dielectric layer. Thus, a reduction in the operational speed of a semiconductor device having transistors can be prevented.

15. 发明授权

US06214676B1 Embedded memory logic device using self-aligned silicide and manufacturing method therefor 有权
标题翻译：使用自对准硅化物的嵌入式存储器逻辑器件及其制造方法
公开(公告)号：US06214676B1
公开(公告)日：2001-04-10
申请号：US09506840
申请日：2000-02-18
申请人： In-kyun Jun , Young-pil Kim , Hyung-moo Park , Myeon-koo Kang
发明人： In-kyun Jun , Young-pil Kim , Hyung-moo Park , Myeon-koo Kang
IPC分类号： H01L21336
CPC分类号： H01L27/10894 , H01L27/10873 , H01L27/10888 , H01L27/11
摘要： The operating speed and refresh characteristics of an embedded memory logic device having a silicide layer is improved by excluding the silicide from the source/drain region between access gates and pass gates in a cell array region, thereby reducing leakage current. The source/drain region between access gates and pass gates are also lightly doped to further reduce leakage current. An embedded memory logic device fabricated in accordance with the present invention includes a semiconductor substrate including first and second regions. A first gate electrode is formed over the first region. A first drain region doped with a first impurity is formed in the semiconductor substrate on one side of the first gate electrode, and a first source doped with a second impurity is formed in the semiconductor substrate on the other side of the first gate electrode. A second gate electrode is formed on a second region of the semiconductor substrate, and second source/drain regions doped with a third impurity are formed in the semiconductor substrate on both sides of the second gate electrode. Also, a third gate electrode is formed on the second region of the semiconductor substrate, and third source/drain regions doped with a fourth impurity are formed on both sides of the third gate electrode. Metal silicide layers are formed on the first through third gate electrodes, on the first drain region, and on the second and third source/drain regions.
摘要翻译：具有硅化物层的嵌入式存储器逻辑器件的工作速度和刷新特性通过从栅极阵列区域中的栅极和栅极之间的源极/漏极区域排除硅化物来改善，从而减少漏电流。存取栅极和栅极之间的源极/漏极区域也被轻掺杂，以进一步减少漏电流。根据本发明制造的嵌入式存储器逻辑器件包括包括第一和第二区域的半导体衬底。在第一区域上形成第一栅电极。掺杂有第一杂质的第一漏区形成在第一栅电极的一侧的半导体衬底中，并且在第一栅电极的另一侧上的半导体衬底中形成掺杂有第二杂质的第一源。第二栅电极形成在半导体衬底的第二区域上，并且掺杂有第三杂质的第二源极/漏极区域形成在第二栅电极两侧的半导体衬底中。此外，在半导体衬底的第二区域上形成第三栅电极，在第三栅电极的两侧形成掺杂有第四杂质的第三源/漏区。金属硅化物层形成在第一至第三栅极电极，第一漏极区域以及第二和第三源极/漏极区域上。

16. 发明授权

US5631185A Method for manufacturing capacitor of semiconductor memory device 失效
标题翻译：制造半导体存储器件的电容器的方法
公开(公告)号：US5631185A
公开(公告)日：1997-05-20
申请号：US499327
申请日：1995-07-07
申请人： Young-pil Kim , Jong-bok Kim , Kweon-jae Lee
发明人： Young-pil Kim , Jong-bok Kim , Kweon-jae Lee
IPC分类号： H01L27/08 , H01L21/02 , H01L21/8242 , H01L27/06 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/87
摘要： A method for manufacturing a capacitor of a semiconductor memory device is provided. A first insulating layer and a second insulating layer are formed in sequence on a semiconductor substrate on which a transistor including a source region, a drain region and a gate electrode, and a buried bit-line surrounded by insulating layer are formed. Then, a contact hole is formed by sequentially etching the layers stacked on the source region, by which the source region of the transistor is exposed, and a spacer made of an insulating substance is formed inside the contact hole, and a first conductive layer is formed on the whole surface of the resultant. Next, the first conductive layer and second insulating layer are etched, and a second conductive layer is formed on the whole surface of the resultant, and a storage electrode is formed by etching the second conductive layer using the first conductive layer as a mask. According to the method, the step for forming the contact hole is very simple and less photolithography steps are required since the first conductive layer is used as a mask for etching the second conductive layer, thereby simplifying the manufacturing process.
摘要翻译：提供一种制造半导体存储器件的电容器的方法。在半导体衬底上依次形成第一绝缘层和第二绝缘层，在半导体衬底上形成包括源极区，漏极区和栅电极的晶体管，以及由绝缘层包围的掩埋位线。然后，通过依次蚀刻堆叠在源区域上的层，形成晶体管的源极区域而暴露的层，并且在接触孔内部形成由绝缘物质构成的间隔物，并且第一导电层为形成在所得物的整个表面上。接下来，蚀刻第一导电层和第二绝缘层，并且在所得的整个表面上形成第二导电层，并且通过使用第一导电层作为掩模蚀刻第二导电层来形成存储电极。根据该方法，用于形成接触孔的步骤非常简单，因为使用第一导电层作为用于蚀刻第二导电层的掩模，因此简化了制造工艺，因此需要较少的光刻步骤。

17. 发明授权

US08406029B2 Identification of data positions in magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices 有权
标题翻译：识别磁包存储器存储设备中的数据位置，包括这种设备的存储器系统以及控制这些设备的方法
公开(公告)号：US08406029B2
公开(公告)日：2013-03-26
申请号：US12658859
申请日：2010-02-16
申请人： Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Jong-wan Kim , Hyun-ho Choi , Young-pil Kim , Sung-chul Lee
发明人： Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Jong-wan Kim , Hyun-ho Choi , Young-pil Kim , Sung-chul Lee
IPC分类号： G11C19/00
CPC分类号： G11C19/0808 , G11C11/14 , G11C19/0841
摘要： In a memory device and in a method for controlling a memory device, the memory device comprises a magnetic structure that stores information in a plurality of domains of the magnetic structure. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure. A position detector unit compares the information read by a read current from the read unit from multiple domains of the plurality of domains of the magnetic structure to identify the presence of an expected information pattern at select domains of the plurality of domains.
摘要翻译：在存储器装置和用于控制存储器件的方法中，存储器件包括将结构存储在磁性结构的多个域中的磁性结构。读取单元通过向磁性结构施加读取电流来从磁性结构的多个域中的至少一个域读取信息。位置检测器单元将来自读取单元的读取电流读取的信息与磁性结构的多个域的多个域进行比较，以识别多个域的选定域处的预期信息模式的存在。

18. 发明授权

US08273620B2 Semiconductor integrated circuit device and related fabrication method 有权
标题翻译：半导体集成电路器件及相关制造方法
公开(公告)号：US08273620B2
公开(公告)日：2012-09-25
申请号：US12793809
申请日：2010-06-04
申请人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
发明人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
IPC分类号： H01L21/8234
CPC分类号： H01L21/823418 , H01L21/823456 , H01L27/105 , H01L27/1052
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由隔离区。半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。

19. 发明申请

US20100208504A1 Identification of data positions in magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices 有权
标题翻译：识别磁包存储器存储设备中的数据位置，包括这种设备的存储器系统以及控制这些设备的方法
公开(公告)号：US20100208504A1
公开(公告)日：2010-08-19
申请号：US12658859
申请日：2010-02-16
申请人： Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Jong-wan Kim , Hyun-ho Choi , Young-pil Kim , Sung-chul Lee
发明人： Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Jong-wan Kim , Hyun-ho Choi , Young-pil Kim , Sung-chul Lee
IPC分类号： G11C19/00 , G11C7/00
CPC分类号： G11C19/0808 , G11C11/14 , G11C19/0841
摘要： In a memory device and in a method for controlling a memory device, the memory device comprises a magnetic structure that stores information in a plurality of domains of the magnetic structure. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure. A position detector unit compares the information read by a read current from the read unit from multiple domains of the plurality of domains of the magnetic structure to identify the presence of an expected information pattern at select domains of the plurality of domains.
摘要翻译：在存储器装置和用于控制存储器件的方法中，存储器件包括将结构存储在磁性结构的多个域中的磁性结构。读取单元通过向磁性结构施加读取电流来从磁性结构的多个域中的至少一个域读取信息。位置检测器单元将来自读取单元的读取电流读取的信息与磁性结构的多个域的多个域进行比较，以识别多个域的选定域处的预期信息模式的存在。

20. 发明授权

US07755133B2 Semiconductor integrated circuit device and related fabrication method 有权
标题翻译：半导体集成电路器件及相关制造方法
公开(公告)号：US07755133B2
公开(公告)日：2010-07-13
申请号：US11855529
申请日：2007-09-14
申请人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
发明人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
IPC分类号： H01L29/788
CPC分类号： H01L21/823418 , H01L21/823456 , H01L27/105 , H01L27/1052
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由隔离区。半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。

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