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    • 11. 发明授权
    • Analog voltage metering system with programmable bit-serial digital
signal processors
    • 具有可编程位串行数字信号处理器的模拟电压计量系统
    • US5448747A
    • 1995-09-05
    • US250122
    • 1994-05-27
    • Steven L. GarverickKenji Fujino
    • Steven L. GarverickKenji Fujino
    • G01R19/00G01R21/00G01R21/133G05B19/042G06F7/544G06F15/78G06F17/10G06F7/38
    • G06F15/7842G05B19/0423G06F7/5443G06F7/5446G01R21/006G05B2219/25254
    • A monolithic integrated circuit as may be used in combination with a plurality of sensors for generating respective sensor output signals, which monolithic integrated circuit includes means for converting each sensor output signal to bit-serial digital format, together with some initial processing circuitry comprising a bit-serial multiply-add processor. This processor includes a bit-serial digital multiplier for multiplying a first digital processor input signal in bit-serial form by a second digital processor input signal to generate a digital product signal, a digital adder for adding a third digital processor input signal to the digital product signal to generate a digital sum signal, and means for supplying a digital processor output signal with bits correspond-ing to those of said digital sum signal. A memory system provides memory for storing program instructions, memory for storing successive values of the second digital processor input signal, memory for storing successive values of the third digital processor input signal, and memory for storing successive values of the digital processor output signal as written into the memory system. The first digital processor input signal can be selected from among the sensor output signals as converted to bit-serial digital format. The second digital processor input signals applied to the bit-serial multiply-add processor are at least at selected times read from the memory system, as are the third digital processor input signals applied to the bit-serial multiply-add processor. A controller retrieves stored program instructions in a prescribed order from the memory for storing program instructions and generates control signals for controlling at least the reading and writing of the memory system, as well as the selecting of the first digital processor input signal.
    • 可以与用于产生各个传感器输出信号的多个传感器组合使用的单片集成电路,该单片集成电路包括用于将每个传感器输出信号转换为位串行数字格式的装置,以及一些初始处理电路,包括一位 - 系列乘法加法处理器。 该处理器包括位串行数字乘法器,用于将位串行形式的第一数字处理器输入信号乘以第二数字处理器输入信号以产生数字乘积信号;数字加法器,用于将第三数字处理器输入信号加到数字 产生信号以产生数字和信号,以及用于向数字处理器输出信号提供与所述数字和信号相对应的位的装置。 存储器系统提供用于存储程序指令的存储器,用于存储第二数字处理器输入信号的连续值的存储器,用于存储第三数字处理器输入信号的连续值的存储器和用于存储数字处理器输出信号的连续值的存储器, 进入内存系统。 可以从传感器输出信号中选择第一个数字处理器输入信号,转换为位串行数字格式。 应用于位串行乘法加法处理器的第二数字处理器输入信号至少在从存储器系统读取的选定时间,以及施加到位串行乘法加法处理器的第三数字处理器输入信号。 控制器从用于存储程序指令的存储器中以规定的顺序检索存储的程序指令,并且生成用于至少控制存储器系统的读取和写入以及第一数字处理器输入信号的选择的控制信号。
    • 12. 发明申请
    • Gene Participating in Low Temperature Germinability in Rice and Utilization of the Same
    • 基因参与水稻的低温发芽率及其利用
    • US20110119790A1
    • 2011-05-19
    • US12676473
    • 2008-09-05
    • Kenji FujinoHiroshi Sekiguch
    • Kenji FujinoHiroshi Sekiguch
    • A01H1/00C07H21/04C07K14/415A01H5/00G01N33/48
    • C07K14/415C12N15/8273
    • The present invention provides a gene participating in the low temperature germinability in rice and utilization of the same, and the invention relates to a gene for a low temperature germinability which is an isolated qLTG-3-1 gene from the rice line Italica Livorno, has low temperature germinability and has the base sequence of SEQ ID NO: 1; an amino acid sequence encoded by the gene; a transgenic plant transformed with the gene for the low temperature germinability to improve the low temperature germinability; a method of analyzing low temperature germinability, including analyzing the low temperature germinability of a cultivar by comparing the base sequence of the gene for the low temperature germinability with the genotype of the cultivar; a method of improving the low temperature germinability of rice, including transforming the gene for the low temperature germinability into a rice cultivar to improve the low temperature germinability of the cultivar under low temperature conditions; and a method of analyzing the low temperature germinability of a rice cultivar by utilizing the expression of the gene for the low temperature germinability.
    • 本发明提供了一种参与水稻低温发芽性的基因及其利用方法,本发明涉及一种低温发芽性基因,该基因是水稻品系Italica Livorno中分离的qLTG-3-1基因,具有 具有低温发芽性,并具有SEQ ID NO:1的碱基序列; 由该基因编码的氨基酸序列; 转基因植物转基因为低温发芽性,提高低温发芽率; 分析低温发芽率的方法,包括通过比较低温发芽能力基因的碱基序列与品种的基因型来分析品种的低温发芽率; 提高水稻低温发芽率的方法,包括将低温发芽基因转化为水稻品种,以提高低温条件下品种的低温发芽率; 以及通过利用该基因表达低温发芽性来分析水稻品种的低温发芽率的方法。
    • 13. 发明授权
    • Etching an optical fiber fusion splice
    • 蚀刻光纤熔接
    • US06553791B1
    • 2003-04-29
    • US09588309
    • 2000-06-06
    • Keiji OsakaKenji Fujino
    • Keiji OsakaKenji Fujino
    • G02B6255
    • G02B6/2558G02B6/25G02B6/2551
    • An exposed part of at least one of two optical fibers with different mode field distributions to be fusion spliced is heated by a burner, to thereby continuously vary its mode field distribution in the longitudinal direction of the optical fiber, and the exposed end part of at least one of the optical fibers is cleaved so that the mode field distributions at the splice end faces of the two optical fibers to be fusion spliced are substantially coincident with each other in configuration, the two optical fibers are fusion spliced, whereby low splice loss is realized. Thereafter, the heated portion of the optical fiber is subjected to a surface treatment by etching process using a hydrofluoric acid solution, whereby a deterioration of its mechanical strength is prevented. Surface tension of the acid causes the rim of the container to stand up.
    • 具有不同模场分布的两个光纤中的至少一个待融合的暴露部分由燃烧器加热,从而连续地改变其在光纤的纵向方向上的模场分布,并且暴露的端部处于 光纤中的至少一个被切割,使得要融合的两个光纤的接合端面处的模场分布在结构上基本一致,两个光纤熔接,由此低的接合损耗为 实现了 此后,通过使用氢氟酸溶液的蚀刻工艺对光纤的加热部分进行表面处理,从而防止其机械强度的劣化。 酸的表面张力使容器的边缘立起来。
    • 15. 发明授权
    • Measuring electrical parameters of power line operation, using a digital
computer
    • 测量电力线操作的电气参数,使用数字电脑
    • US5301121A
    • 1994-04-05
    • US728408
    • 1991-07-11
    • Steven L. GarverickKenji FujinoMasaaki NishijoMasami Imamoto
    • Steven L. GarverickKenji FujinoMasaaki NishijoMasami Imamoto
    • G01R22/00G01R19/00G01R19/25G01R21/133G01R35/04H02J3/00
    • G01R21/1331G01R19/25G01R35/04
    • A method for measuring at least one electrical parameter of the operation of a p-phase power line, p being a positive integer, arranges respective sensing apparatus to sense at least one of the voltages and currents associated with each phase of the power line. Analog-to-digital conversion apparatus is used to digitize the response of each sensing apparatus, thereby to generate corresponding digital responses. A digital computer is used to correct each digitized response of the analog-to-digital conversion apparatus for non-linearities, gain errors and phasing errors in the responses of the sensing apparatus and for non-linearities and gain errors in the responses of the analog-to-digital conversion apparatus. The computer is used to high-pass digitally filter each digital response that has been corrected, in order to suppress any attendant direct term. The digital computer then calculates each the electrical parameter, proceeding from each digital response that has been corrected and has been high-pass digitally filtered.
    • 一种用于测量p相电力线的操作的至少一个电参数的方法,p是正整数,布置各个感测装置以感测与电力线的每个相位相关联的电压和电流中的至少一个。 模拟数字转换装置用于数字化每个感测装置的响应,从而产生相应的数字响应。 使用数字计算机来校正模数转换装置的每个数字化响应,用于感测装置的响应中的非线性,增益误差和相位误差,以及模拟的响应中的非线性和增益误差 数字转换装置。 计算机用于高通数字过滤每个已被纠正的数字响应,以便抑制任何随之而来的直接期限。 然后,数字计算机计算每个电参数,从已经被校正并已被高通数字滤波的每个数字响应开始。
    • 17. 发明申请
    • Image processing apparatus, monitoring camera, and image monitoring system
    • 图像处理设备,监控摄像机和图像监控系统
    • US20070229663A1
    • 2007-10-04
    • US11727082
    • 2007-03-23
    • Teruma AotoKenji FujinoRyousuke KashiwaKazurou Itou
    • Teruma AotoKenji FujinoRyousuke KashiwaKazurou Itou
    • H04N7/18
    • G06K9/00335G06T7/20G06T2207/30241G08B21/043G08B21/0476
    • An image processing apparatus, a monitoring camera, and an image monitoring system are provide which are capable of eliminating false reports made in a motion analysis process to provide more advanced behavior analysis. The image processing apparatus includes: a motion analysis unit which receives a moving image on a monitoring area captured by an external monitoring camera, analyzes a general purpose motion of a person appearing on the monitoring area by performing a predetermined image analysis process to the moving image, and outputs time-series data related to the general purpose motion of the person; and a motion identification unit which identifies, on the basis of the time-series data related to the general purpose motion of the person, whether or not the general purpose motion corresponds to a specific purpose motion that satisfies a predetermined condition, and outputs motion identification information representing the identification result.
    • 提供一种图像处理装置,监视摄像机和图像监视系统,其能够消除在运动分析过程中作出的虚假报告以提供更高级的行为分析。 图像处理装置包括:运动分析单元,其在由外部监视摄像机捕获的监视区域上接收运动图像,通过对运动图像执行预定的图像分析处理来分析出现在监视区域上的人的通用动作 并输出与该人的通用动作有关的时间序列数据; 以及运动识别单元,其基于与人的通用运动相关的时间序列数据来识别通用运动是否对应于满足预定条件的特定运动,并且输出运动识别 表示识别结果的信息。
    • 19. 发明授权
    • Layer-built heat exchanger
    • 层叠式热交换器
    • US5392849A
    • 1995-02-28
    • US200365
    • 1994-02-23
    • Tsuyoshi MatsunagaKenji FujinoTakashi SugaharaHiroaki Kan
    • Tsuyoshi MatsunagaKenji FujinoTakashi SugaharaHiroaki Kan
    • F28D9/00F28F3/08
    • F28D9/0075F28F2280/04
    • A layer-built heat exchanger has channels formed by dividers in a first-side plate 32 and a second-side plate 33. A seal plate 3 is interposed between the first- and second-side plates. The first-side plate 32 and second-side plate 33 are positioned relative to each other such that dividers 35 of the second-side plate 33 are in line with channels 36 of the first-side plate 32, and dividers 34 of the first-side plate 32 are in line with the channels 37 of the second-side plate 33, thus preventing deformation of the seal plate 3 due to a high differential pressure between the coolants flowing through the channels of the first- and second-side plates. The corners of the first-side plate 32, second-side plate 33, and seal plate 3 are also shaped differently so that omission of one of the component plates can be easily confirmed.
    • 层叠式热交换器具有在第一侧板32和第二侧板33中由分隔件形成的通道。密封板3插入在第一和第二侧板之间。 第一侧板32和第二侧板33相对于彼此定位,使得第二侧板33的分隔件35与第一侧板32的通道36成一直线, 侧板32与第二侧板33的通道37一致,从而防止密封板3由于流经第一和第二侧板的通道的冷却剂之间的高压差而发生变形。 第一侧板32,第二侧板33和密封板3的角部也被不同地成形,从而可以容易地确认省略其中一个部件板。