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11. 发明申请

US20050024811A1 Semiconductor device with adhesion-improvement capacitor and process for producing the device 失效
标题翻译：具有粘附改善电容器的半导体器件及其制造方法
公开(公告)号：US20050024811A1
公开(公告)日：2005-02-03
申请号：US10923002
申请日：2004-08-23
申请人： Hiroshi Moriya , Tomio Iwasaki , Hiroyuki Ohta , Shinpei Iijima , Isamu Asano , Yuzuru Ohji , Yoshitaka Nakamura
发明人： Hiroshi Moriya , Tomio Iwasaki , Hiroyuki Ohta , Shinpei Iijima , Isamu Asano , Yuzuru Ohji , Yoshitaka Nakamura
IPC分类号： H01L27/10 , H01L21/02 , H01L21/8242 , H01L27/108 , H01G4/008
CPC分类号： H01L28/60 , H01L27/10814 , H01L28/55
摘要： A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.
摘要翻译：一种配备有信息存储电容器的半导体器件，包括第一电容器电极，氧化物膜，第二电容器电极和以硅为主要构成元素的绝缘膜，其中，第一和第二电容器电极中的至少一个包含作为主要构成元素选自铑，钌，铱，锇和铂中的至少一种元素，并且作为添加元素，选自钯，镍，钴和钛中的至少一种元素，电容器电极和绝缘膜之间的粘附性优异。

12. 发明授权

US06696337B2 Method of manufacturing a semiconductor integrated circuit device having a memory cell array and a peripheral circuit region 有权
标题翻译：具有存储单元阵列和外围电路区域的半导体集成电路器件的制造方法
公开(公告)号：US06696337B2
公开(公告)日：2004-02-24
申请号：US10166013
申请日：2002-06-11
申请人： Isamu Asano , Robert Tsu
发明人： Isamu Asano , Robert Tsu
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L27/10814 , H01L27/10844 , H01L27/10852 , H01L27/10885 , H01L27/10897
摘要： In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors. A position at which a transistor for selectively connecting the memory cell portion and the peripheral circuit portion is formed may be a boundary, or a position inside a boundary region between the memory cell portion and the peripheral circuit portion may be a boundary, where the thickness change is effected.
摘要翻译：在具有形成在半导体衬底的主表面的第一部分处的存储单元部分和形成在半导体衬底的主表面的第二部分的外围电路部分的DRAM的半导体集成电路器件中，位线导体和第一用于连接存储单元部分和外围电路部分以便在它们之间交换信号的外围电路部分中的高级互连导体由同时形成并因此存在于同一水平的导体层构成。导体层存在于诸如周边电路部分的存储单元部分的外部位置，并且构成外围电路部分的第一级互连导体的导体层的部分的厚度大于外围电路部分的厚度构成位线导体的导体层。形成用于选择性地连接存储单元部分和外围电路部分的晶体管的位置可以是边界，或者存储单元部分和外围电路部分之间的边界区域内的位置可以是边界，其中厚度改变了。

13. 发明授权

US06686619B2 Dynamic random access memory with improved contact arrangements 失效
标题翻译：动态随机存取存储器，具有改进的接触布置
公开(公告)号：US06686619B2
公开(公告)日：2004-02-03
申请号：US10137426
申请日：2002-05-03
申请人： Yoshitaka Nakamura , Hideo Aoki , Yoshikazu Ohira , Tadashi Umezawa , Satoru Yamada , Keizou Kawakita , Isamu Asano , Naoki Fukuda , Tsuyoshi Tamaru , Hidekazu Goto , Nobuyoshi Kobayashi
发明人： Yoshitaka Nakamura , Hideo Aoki , Yoshikazu Ohira , Tadashi Umezawa , Satoru Yamada , Keizou Kawakita , Isamu Asano , Naoki Fukuda , Tsuyoshi Tamaru , Hidekazu Goto , Nobuyoshi Kobayashi
IPC分类号： H01L27108
CPC分类号： H01L27/10894 , H01L21/28518 , H01L21/32053 , H01L21/76843 , H01L21/76855 , H01L21/76889 , H01L21/76897 , H01L27/10885 , H01L28/91 , Y10S257/908
摘要： A semiconductor integrated circuit device and a manufacturing method therefor provide advantages that undulations are prevented from being produced in polycrystal silicon plugs in bit line contact holes and that the undesired phenomenon of transversally etching silicide film at contacts of the bit lines and the polycrystal silicon plugs is avoided. The bit lines formed when forming a first wiring layer are made of a laminate film having a titanium film, a titanium nitride film and a tungsten film, and a titanium silicide film containing nitrogen or oxygen is formed in contact areas of the bit lines and plugs. A titanium silicide film containing nitrogen or oxygen is also formed in contact areas of the first wiring layer and semiconductor substrate. The titanium silicide film may be replaced by silicide film containing nitrogen or oxygen, cobalt silicide film containing nitrogen or oxygen or cobalt silicide film.
摘要翻译：一种半导体集成电路器件及其制造方法，提供了防止在位线接触孔中的多晶硅插塞中产生起伏的优点，并且在位线和多晶硅插头的触点处横向蚀刻硅化物膜的不期望的现象是避免。在形成第一布线层时形成的位线由具有钛膜，氮化钛膜和钨膜的层叠膜制成，并且在位线和插塞的接触区域中形成含有氮或氧的硅化钛膜。含有氮或氧的硅化钛膜也形成在第一布线层和半导体衬底的接触区域中。硅化钛膜可以由含有氮或氧的硅化物膜，含有氮的硅化钴膜或氧化硅或硅化钴膜代替。

14. 发明授权

US06503819B2 Fabrication process of a semiconductor integrated circuit device 有权
公开(公告)号：US06503819B2
公开(公告)日：2003-01-07
申请号：US09773000
申请日：2001-01-31
申请人： Yoshikazu Tanabe , Isamu Asano , Makoto Yoshida , Naoki Yamamoto , Masayoshi Saito , Nobuyoshi Natsuaki
发明人： Yoshikazu Tanabe , Isamu Asano , Makoto Yoshida , Naoki Yamamoto , Masayoshi Saito , Nobuyoshi Natsuaki
IPC分类号： H01L213205
CPC分类号： H01L21/28247 , H01L21/28061 , H01L21/28176 , H01L21/32105 , H01L21/823437 , H01L21/823468 , H01L21/823828 , H01L21/823857 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L29/4941
摘要： With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.

15. 发明授权

US06329681B1 Semiconductor integrated circuit device and method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06329681B1
公开(公告)日：2001-12-11
申请号：US09215270
申请日：1998-12-18
申请人： Yoshitaka Nakamura , Hideo Aoki , Yoshikazu Ohira , Tadashi Umezawa , Satoru Yamada , Keizou Kawakita , Isamu Asano , Naoki Fukuda , Tsuyoshi Tamaru , Hidekazu Goto , Nobuyoshi Kobayashi
发明人： Yoshitaka Nakamura , Hideo Aoki , Yoshikazu Ohira , Tadashi Umezawa , Satoru Yamada , Keizou Kawakita , Isamu Asano , Naoki Fukuda , Tsuyoshi Tamaru , Hidekazu Goto , Nobuyoshi Kobayashi
IPC分类号： H01L27108
CPC分类号： H01L27/10894 , H01L21/28518 , H01L21/32053 , H01L21/76843 , H01L21/76855 , H01L21/76889 , H01L21/76897 , H01L27/10885 , H01L28/91 , Y10S257/908
摘要： A semiconductor integrated circuit device and a method of manufacturing such a device provides the advantages that undulations are prevented from being produced in the polycrystal silicon plugs in the bit line contact holes and that the undesired phenomenon of transversally etching the silicide film at the contacts of the bit lines and the polycrystal silicon plugs is avoided. The bit lines BL formed at the time of forming a first wiring layer 18 is made of a laminate film having a titanium film 18a, a titanium nitride film 18b and a tungsten film 18c and a titanium silicide film 20 containing nitrogen or oxygen is formed in the contact areas of the bit lines BL and the plugs 19. A titanium silicide film 20 containing nitrogen or oxygen is also formed in the contact areas of the first wiring layer 18 and the semiconductor substrate 1. The titanium silicide film 20 may be replaced by a tungsten silicide film containing nitrogen or oxygen, a cobalt silicide film containing nitrogen or oxygen or a cobalt silicide film.
摘要翻译：半导体集成电路器件和这种器件的制造方法提供了这样的优点：防止在位线接触孔中的多晶硅插塞中产生起伏，并且在触点处的触点处横向蚀刻硅化物膜的不期望的现象避免了位线和多晶硅插头。在形成第一布线层18时形成的位线BL由具有钛膜18a，氮化钛膜18b和钨膜18c的层压膜和含有氮或氧的硅化钛膜20形成位线BL和插头19的接触面积。也可以在第一布线层18和半导体衬底1的接触区域中形成含有氮或氧的硅化钛膜20.硅化钛膜20可以由含有氮或氧的硅化钨膜，含有氮或氧的硅化钴膜或硅化钴膜。

16. 发明授权

US06294420B1 Integrated circuit capacitor 失效
标题翻译：集成电路电容
公开(公告)号：US06294420B1
公开(公告)日：2001-09-25
申请号：US09014724
申请日：1998-01-28
申请人： Robert Tsu , Isamu Asano , Shinpei Iijima , William R. McKee
发明人： Robert Tsu , Isamu Asano , Shinpei Iijima , William R. McKee
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/28518 , H01L21/76897 , H01L28/55 , H01L28/90
摘要： The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon or a metal. A layer 28 of a first material, such as a siliciding metal, is formed over the base electrode 18 as well as the adjacent insulating region. A self-aligned capacitor electrode 12 can then be formed by reacting the first material 28 with the base electrode 18 and removing unreacted portions of the first material 28 from the insulating region 26. The capacitor is then completed by forming a dielectric layer 16 over the self-aligned capacitor electrode 12 and a second capacitor electrode 14 over the dielectric layer 16.
摘要翻译：本发明公开了一种新颖的集成电路电容器及其形成方法。电容器形成从邻近绝缘区域26的基极18开始。该基极18可以包括多晶硅或金属。诸如硅化金属的第一材料的层28形成在基极电极18上以及相邻的绝缘区域上。然后可以通过使第一材料28与基底电极18反应并从绝缘区域26去除第一材料28的未反应部分来形成自对准电容器电极12.然后通过在电容器电极12上形成介电层16来完成电容器自对准电容器电极12和在电介质层16上的第二电容器电极14。

17. 发明授权

US06197702B1 Fabrication process of a semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造工艺
公开(公告)号：US06197702B1
公开(公告)日：2001-03-06
申请号：US09086568
申请日：1998-05-29
申请人： Yoshikazu Tanabe , Isamu Asano , Makoto Yoshida , Naoki Yamamoto , Masayoshi Saito , Nobuyoshi Natsuaki
发明人： Yoshikazu Tanabe , Isamu Asano , Makoto Yoshida , Naoki Yamamoto , Masayoshi Saito , Nobuyoshi Natsuaki
IPC分类号： H01L2131
CPC分类号： H01L21/28247 , H01L21/28061 , H01L21/28176 , H01L21/32105 , H01L21/823437 , H01L21/823468 , H01L21/823828 , H01L21/823857 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L29/4941
摘要： With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.
摘要翻译：为了在栅极图案化之后防止光氧化处理时的金属膜的氧化，同时可以控制氧化膜形成的再现性和栅极侧壁端的氧化膜厚度的均匀性在使用多金属的栅极处理步骤中，通过图案化已经沉积在其上形成有栅极氧化膜的半导体晶片1A上并具有多金属结构的栅电极材料来形成栅电极，加热到预定温度或其附近的半导体晶片1A的主表面被供给含有低浓度的水的氢气，通过催化作用由氢和氧形成的水，以选择性地氧化主表面从而提高了栅电极的侧壁端部的形状。

18. 发明授权

US06169324A Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
标题翻译：半导体集成电路装置及其制造方法及其制造装置
公开(公告)号：US06169324A
公开(公告)日：2001-01-02
申请号：US09413754
申请日：1999-10-06
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： H01L2144
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L24/45 , H01L24/48 , H01L27/0922 , H01L27/0928 , H01L27/10808 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

19. 发明授权

US5930624A Method of producing semiconductor integrated circuit device having switching MISFET and capacitor element including wiring 失效
标题翻译：具有开关MISFET和包括布线的电容元件的半导体集成电路器件的制造方法
公开(公告)号：US5930624A
公开(公告)日：1999-07-27
申请号：US13605
申请日：1998-01-26
申请人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
发明人： Jun Murata , Yoshitaka Tadaki , Isamu Asano , Mitsuaki Horiuchi , Jun Sugiura , Hiroko Kaneko , Shinji Shimizu , Atsushi Hiraiwa , Hidetsugu Ogishi , Masakazu Sagawa , Masami Ozawa , Toshihiro Sekiguchi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/105 , H01L27/108
CPC分类号： H01L27/105 , H01L27/10808
摘要： A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, is disclosed. In a first aspect, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In other aspects, a Y-select signal line overlaps the lower electrode layer of the capacitor element; a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected, is formed by diffusion of an impurity for a channel stopper region; the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it, the capacitor dielectric film being a silicon nitride film having a silicon oxide layer thereon, the silicon oxide layer being formed by oxidizing a surface layer of the silicon nitride under high pressure; an aluminum wiring layer and a protective (and/or barrier) layer are formed by sputtering in the same vacuum sputtering chamber without breaking the vacuum between forming the layers; and a refractory metal, or a refractory metal silicide, is used as the protective layer for an aluminum wiring containing an added element (e.g., Cu) to prevent migration.
摘要翻译：公开了一种具有开关MISFET的半导体集成电路器件和形成在半导体衬底上的电容器元件。在第一方面中，电容器元件连接的开关MISFET的半导体区域的杂质浓度小于外围电路的MISFET的半导体区域的杂质浓度。在其他方面，Y选择信号线与电容器元件的下电极层重叠; 至少在与电容器元件连接的开关MISFET的半导体区域下方设置的势垒层通过用于沟道阻挡区域的杂质的扩散而形成; 电容器元件的电介质膜与其上的电容器电极层共同扩展，电容器电介质膜是其上具有氧化硅层的氮化硅膜，氧化硅层通过氧化氮化硅的表面层而形成在高压下通过溅射在相同的真空溅射室中形成铝布线层和保护（和/或阻挡层），而不破坏形成层之间的真空; 和难熔金属或难熔金属硅化物用作用于包含添加元素（例如Cu）以防止迁移的铝布线的保护层。

20. 发明授权

US5780882A Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
公开(公告)号：US5780882A
公开(公告)日：1998-07-14
申请号：US456788
申请日：1995-06-01
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L27/02
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

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