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11. 发明授权

US5844840A High voltage NMOS pass gate having supply range, area, and speed advantages 失效
标题翻译：具有供电范围，面积和速度优势的高压NMOS通道门
公开(公告)号：US5844840A
公开(公告)日：1998-12-01
申请号：US914543
申请日：1997-08-19
申请人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Chung-You Hu , Narbeh Derhacobian
发明人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Chung-You Hu , Narbeh Derhacobian
IPC分类号： G11C8/08 , G11C16/06
CPC分类号： G11C8/08
摘要： According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistors threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.
摘要翻译：根据实施例的一个方面，驱动用于闪存阵列的字线的传输晶体管的块解码器控制电路被控制电压驱动，该控制电压被调节为高于最高电压的一个增强晶体管阈值电压实际上驱动到字线上。根据一些实施例的另一方面，块解码器控制电路用具有非常低的阈值电压的晶体管来实现。根据一些实施例的另一方面，使用特殊的串联连接来防止任何来自块解码器控制电路的泄漏电流与由高阈值电压晶体管使用而产生的高电压产生电荷泵。在特殊的串联连接中，从电源电压源而不是高压发生电荷泵发生泄漏电流。根据一些实施例的另一方面，特殊栅极连接将高于正电源电压的中间偏置电压施加到连接到高电压的未选择的块解码器晶体管的栅极上。提出了组合调节的控制电压方面和其他方面的各种组合的几个实施例。

12. 发明授权

US06798275B1 Fast, accurate and low power supply voltage booster using A/D converter 有权
标题翻译：使用A / D转换器的快速，准确和低电源电压升压器
公开(公告)号：US06798275B1
公开(公告)日：2004-09-28
申请号：US10406415
申请日：2003-04-03
申请人： Binh Quang Le , Cathy Thuvan Ly , Lee Cleveland , Pau-Ling Chen
发明人： Binh Quang Le , Cathy Thuvan Ly , Lee Cleveland , Pau-Ling Chen
IPC分类号： G05F110
CPC分类号： G11C5/145 , G11C8/08
摘要： Flash memory array systems and methods are disclosed for producing a regulated boosted word line voltage for read operations. The system comprises a multi-stage voltage boost circuit operable to receive a supply voltage and one or more output signals from a supply voltage detection circuit to generate the boosted word line voltage having a value greater than the supply voltage. The voltage boost circuit comprises a precharge circuit and a plurality of boost cells connected to a common node of the boosted word line, and a timing control circuit. The stages of the plurality of boost cells are coupled in series for charge sharing between the stages, and couple a predetermined number of boost cells to the boosted word line common node to provide an intermediate voltage to the boosted word line during the pre-boost timing, thereby anticipating a final boosted word line voltage provided during the boost timing. The voltage boost circuit is operable to receive the one or more output signals from the supply voltage detection circuit and alter a boost gain of the multi-stage voltage boost circuit based on the one or more output signals, thereby causing the boosted word line voltage to be substantially independent of the supply voltage value.
摘要翻译：公开了闪存阵列系统和方法，用于产生用于读取操作的稳压升压字线电压。该系统包括多级升压电路，其可操作以从电源电压检测电路接收电源电压和一个或多个输出信号，以产生具有大于电源电压的值的升压字线电压。升压电路包括预充电电路和连接到升压字线的公共节点的多个升压单元以及定时控制电路。多个升压单元的级级串联耦合，用于级之间的电荷共享，并且将预定数量的升压单元耦合到升压字线公共节点，以在预升压定时期间向升压的字线提供中间电压从而预期在升压定时期间提供的最后升高的字线电压。电压升压电路可操作以从电源电压检测电路接收一个或多个输出信号，并且基于一个或多个输出信号改变多级升压电路的升压增益，从而使升压的字线电压基本上不依赖于电源电压值。

13. 发明授权

US06304487B1 Register driven means to control programming voltages 有权
标题翻译：寄存器驱动方式来控制编程电压
公开(公告)号：US06304487B1
公开(公告)日：2001-10-16
申请号：US09514404
申请日：2000-02-28
申请人： Joseph G. Pawletko , Binh Quang Le , Pau-Ling Chen , James M. Hong
发明人： Joseph G. Pawletko , Binh Quang Le , Pau-Ling Chen , James M. Hong
IPC分类号： G11C1606
CPC分类号： G11C16/12 , G11C16/10 , G11C16/3436
摘要： A voltage control circuit that programs or erases memory cells comprises an internal voltage value store, a register device selectively coupled to an external voltage value source or the internal voltage value store to receive a voltage value, a voltage output circuit coupled to the register device to receive the voltage value and to output a corresponding voltage to the memory cells, and a verify circuit determining the time to successfully program or erase the memory cells. The register device allows the memory cells to be programmed or erased with voltage values designated by the external voltage value source to determine programming and erasing characteristics of the memory cells. Voltage values producing acceptable programming and erasing characteristics are saved in the internal voltage value store.
摘要翻译：编程或擦除存储器单元的电压控制电路包括内部电压值存储器，选择性地耦合到外部电压值源的寄存器器件或用于接收电压值的内部电压值存储器，耦合到寄存器器件的电压输出电路，接收电压值并将相应的电压输出到存储器单元，以及确认电路确定成功编程或擦除存储单元的时间。寄存器件允许用由外部电压值源指定的电压值对存储器单元进行编程或擦除，以确定存储器单元的编程和擦除特性。产生可接受的编程和擦除特性的电压值被保存在内部电压值存储器中。

14. 发明授权

US06246611B1 System for erasing a memory cell 有权
标题翻译：擦除存储单元的系统
公开(公告)号：US06246611B1
公开(公告)日：2001-06-12
申请号：US09514560
申请日：2000-02-28
申请人： Joseph G. Pawletko , Binh Quang Le , James M. Hong , Pau-Ling Chen
发明人： Joseph G. Pawletko , Binh Quang Le , James M. Hong , Pau-Ling Chen
IPC分类号： G11C1600
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/344
摘要： An erase control circuit erases a memory cell in accordance to an erase signal value that can be varied by a test equipment. The erase control circuit comprises a signal storage device, a signal output circuit, and a verification circuit. The signal storage device stores the erase signal value. A test equipment can be coupled to the signal storage device to write the programming signal value into the signal storage device. The signal output circuit is coupled to the signal storage device to receive the erase signal value. The signal output circuit converts the erase signal value into an erase signal and outputs the erase signal to the memory cell. The verification circuit determines whether the memory cell is successfully erased. If the memory cell is not successfully erased, the erase control circuit increases the erase signal value.
摘要翻译：擦除控制电路根据可由测试设备改变的擦除信号值来擦除存储单元。擦除控制电路包括信号存储装置，信号输出电路和验证电路。信号存储装置存储擦除信号值。测试设备可以耦合到信号存储设备，以将编程信号值写入信号存储设备。信号输出电路耦合到信号存储装置以接收擦除信号值。信号输出电路将擦除信号值转换成擦除信号，并将该擦除信号输出到存储单元。验证电路确定存储器单元是否被成功擦除。如果存储单元未成功擦除，则擦除控制电路增加擦除信号值。

15. 发明授权

US5909396A High voltage NMOS pass gate having supply range, area, and speed advantages 有权
标题翻译：具有供电范围，面积和速度优势的高压NMOS通道门
公开(公告)号：US5909396A
公开(公告)日：1999-06-01
申请号：US127991
申请日：1998-08-03
申请人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Chung-You Hu , Narbeh Derhacobian
发明人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Chung-You Hu , Narbeh Derhacobian
IPC分类号： G11C8/08 , G11C16/06
CPC分类号： G11C8/08
摘要： According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistor's threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.
摘要翻译：根据实施例的一个方面，驱动用于闪存阵列的字线的传输晶体管的块解码器控制电路被控制电压驱动，该控制电压被调节为高于最高电压的一个增强晶体管的阈值电压实际上驱动到字线上。根据一些实施例的另一方面，块解码器控制电路用具有非常低的阈值电压的晶体管来实现。根据一些实施例的另一方面，使用特殊的串联连接来防止任何来自块解码器控制电路的泄漏电流与由高阈值电压晶体管使用而产生的高电压产生电荷泵。在特殊的串联连接中，从电源电压源而不是高压发生电荷泵发生泄漏电流。根据一些实施例的另一方面，特殊栅极连接将高于正电源电压的中间偏置电压施加到连接到高电压的未选择的块解码器晶体管的栅极上。提出了组合调节的控制电压方面和其他方面的各种组合的几个实施例。

16. 发明授权

US5852576A High voltage NMOS pass gate for integrated circuit with high voltage generator and flash non-volatile memory device having the pass gate 失效
标题翻译：具有高电压发生器的集成电路的高电压NMOS通过栅极和具有通过栅极的闪存非易失性存储器件
公开(公告)号：US5852576A
公开(公告)日：1998-12-22
申请号：US944904
申请日：1997-10-06
申请人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Shoichi Kawamura , Michael Shingche Chung , Vincent C. Leung , Masaru Yano
发明人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Shoichi Kawamura , Michael Shingche Chung , Vincent C. Leung , Masaru Yano
IPC分类号： G11C16/06 , G11C8/08 , G11C16/12 , G11C13/00
CPC分类号： G11C16/12 , G11C8/08
摘要： Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply. By setting the decode input at zero volts, the voltages at the gates of the boost transistors and of the pass transistor are held at zero volts, thus disabling them. In the preferred embodiment, both the regulation transistors and the discharge transistors are included in the high voltage pass gate.
摘要翻译：两个NMOS升压晶体管的源极连接到高压输入端，而它们的漏极和栅极交叉连接。两个耦合电容器将两个交替相位时钟连接到两个交叉连接的升压晶体管的栅极。 NMOS传输晶体管的栅极连接到一个NMOS升压晶体管的漏极，其源极连接到高压输入，其漏极连接到输出。在一个实施例中，两个二极管连接的调节晶体管将升压晶体管的栅极连接到高电压输入。这些连接确保升压晶体管的栅极和传输晶体管的栅极不会达到高于高电压输入以上的一个阈值电压的电压。在另一个实施例中，两个放电晶体管的漏极连接到解码输入，其源极连接到升压晶体管的栅极，并且其栅极连接到正电源。通过将解码输入设置为零伏特，升压晶体管和传输晶体管的栅极处的电压保持在零伏特，从而禁止它们。在优选实施例中，调节晶体管和放电晶体管都包括在高压通栅中。

17. 发明授权

US5801579A High voltage NMOS pass gate for integrated circuit with high voltage generator 失效
标题翻译：高电压NMOS栅极，用于集成电路与高压发生器
公开(公告)号：US5801579A
公开(公告)日：1998-09-01
申请号：US808237
申请日：1997-02-28
申请人： Binh Quang Le , Pau-Ling Chen , Shane Hollmer , Shoichi Kawamura , Michael Chung , Vincent Leung , Masaru Yano
发明人： Binh Quang Le , Pau-Ling Chen , Shane Hollmer , Shoichi Kawamura , Michael Chung , Vincent Leung , Masaru Yano
IPC分类号： G11C8/08 , G11C16/12 , G05F1/10
CPC分类号： G11C16/12 , G11C8/08
摘要： Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply. By setting the decode input at zero volts, the voltages at the gates of the boost transistors and of the pass transistor are held at zero volts, thus disabling them. In the preferred embodiment, both the regulation transistors and the discharge transistors are included in the high voltage pass gate.
摘要翻译：两个NMOS升压晶体管的源极连接到高压输入端，而它们的漏极和栅极交叉连接。两个耦合电容器将两个交替相位时钟连接到两个交叉连接的升压晶体管的栅极。 NMOS传输晶体管的栅极连接到一个NMOS升压晶体管的漏极，其源极连接到高压输入，其漏极连接到输出。在一个实施例中，两个二极管连接的调节晶体管将升压晶体管的栅极连接到高电压输入。这些连接确保升压晶体管的栅极和传输晶体管的栅极不会达到高于高电压输入以上的一个阈值电压的电压。在另一个实施例中，两个放电晶体管的漏极连接到解码输入，其源极连接到升压晶体管的栅极，并且其栅极连接到正电源。通过将解码输入设置为零伏特，升压晶体管和传输晶体管的栅极处的电压保持在零伏特，从而禁止它们。在优选实施例中，调节晶体管和放电晶体管都包括在高压通栅中。

18. 发明授权

US06781417B1 Buffer driver circuit for producing a fast, stable, and accurate reference voltage 有权
标题翻译：缓冲驱动电路，用于产生快速，稳定，准确的参考电压
公开(公告)号：US06781417B1
公开(公告)日：2004-08-24
申请号：US10282459
申请日：2002-10-29
申请人： Binh Quang Le , Lee Cleveland , Pau-Ling Chen
发明人： Binh Quang Le , Lee Cleveland , Pau-Ling Chen
IPC分类号： H03K19185
CPC分类号： G05F3/242 , H03K19/018507
摘要： According to one exemplary embodiment, a buffer circuit is configured to receive a supply voltage and an input reference voltage, the buffer circuit has a first FET operating in saturation region where the source of the first FET is coupled to the output reference voltage. The first FET can be configured, for example, as an open-loop voltage follower and, by way of example, a first resistor can be used to couple the source of the first FET to the output reference voltage. A tracking circuit is connected to the buffer circuit. The tracking circuit comprises a second FET also operating in saturation region where the drain of the second FET is coupled to the output reference voltage. Both the first and second FETs can be, for example, depletion mode transistors.
摘要翻译：根据一个示例性实施例，缓冲电路被配置为接收电源电压和输入参考电压，所述缓冲电路具有在饱和区域中工作的第一FET，其中第一FET的源极耦合到输出参考电压。第一FET可以被配置为例如开环电压跟随器，并且作为示例，可以使用第一电阻器将第一FET的源极耦合到输出参考电压。跟踪电路连接到缓冲电路。跟踪电路包括也在饱和区域工作的第二FET，其中第二FET的漏极耦合到输出参考电压。第一和第二FET都可以是例如耗尽型晶体管。

19. 发明授权

US06700815B2 Refresh scheme for dynamic page programming 有权
标题翻译：动态页面编程刷新方案
公开(公告)号：US06700815B2
公开(公告)日：2004-03-02
申请号：US10119273
申请日：2002-04-08
申请人： Binh Quang Le , Michael Chung , Pau-Ling Chen
发明人： Binh Quang Le , Michael Chung , Pau-Ling Chen
IPC分类号： G11C1604
CPC分类号： G11C16/3431 , G11C16/0475 , G11C16/3418
摘要： A flash memory array having multiple dual bit memory cells divided into section attached to a wordline and a pair of reference cells logically associated with each section. A method of reprogramming a section or sections of words that are required to be changed includes inputting allowed changes to the flash memory array, reading word or words to be changed in each section, programming bits in word or words to be changed in each section, refreshing previously programmed bits in the word or words that are changed, refreshing previously programmed bits in the word or words changed in each section, refreshing previously programmed bits in the remaining word or words in each section and refreshing previously programmed in each pair of reference cells in the section in which changes have been made.
摘要翻译：一种闪存阵列，其具有被分成连接到字线的部分和与每个部分逻辑关联的一对参考单元的多个双位存储器单元。重新编程需要改变的单词部分或方式的方法包括：输入对闪存阵列的允许的改变，读取每个部分中要改变的单词或单词，在每个部分中改变单词或单词中的位，刷新改变的单词中的先前编程的位，刷新每个部分中改变的单词中改变的先前编程的比特，刷新每个部分中剩余单词或先前编程的比特，并刷新以前在每对参考单元中编程在作出改变的部分。

20. 发明授权

US5978267A Bit line biasing method to eliminate program disturbance in a non-volatile memory device and memory device employing the same 有权
标题翻译：位线偏置方法，用于消除非易失性存储器件和采用其中的存储器件中的程序干扰
公开(公告)号：US5978267A
公开(公告)日：1999-11-02
申请号：US175647
申请日：1998-10-20
申请人： Pau-Ling Chen , Michael Van Buskirk , Shane C. Hollmer , Michael S. C. Chung , Binh Quang Le , Vincent Leung , Shoichi Kawamura , Masaru Yano
发明人： Pau-Ling Chen , Michael Van Buskirk , Shane C. Hollmer , Michael S. C. Chung , Binh Quang Le , Vincent Leung , Shoichi Kawamura , Masaru Yano
IPC分类号： G11C16/02 , G11C7/12 , G11C16/04 , G11C16/06 , G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C7/12
摘要： In the programming of a non-volatile memory device, such as a NAND flash memory device 100, a positive bias voltage V.sub.bias is applied to a bit line 44 to set a respective memory gate 44a in a programmed state. In a further embodiment, the positive bias voltage V.sub.bias is obtained by dividing the select drain gate voltage V.sub.cc using two resistors 56 and 58 connected in series.
摘要翻译：在非易失性存储器件（例如NAND闪速存储器件100）的编程中，将正偏置电压Vbias施加到位线44以将相应的存储器栅极44a设置为编程状态。在另一实施例中，通过使用串联连接的两个电阻器56和58分压选择漏极栅极电压Vcc来获得正偏置电压Vbias。

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