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1. 发明授权

US5852576A High voltage NMOS pass gate for integrated circuit with high voltage generator and flash non-volatile memory device having the pass gate 失效
标题翻译：具有高电压发生器的集成电路的高电压NMOS通过栅极和具有通过栅极的闪存非易失性存储器件
公开(公告)号：US5852576A
公开(公告)日：1998-12-22
申请号：US944904
申请日：1997-10-06
申请人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Shoichi Kawamura , Michael Shingche Chung , Vincent C. Leung , Masaru Yano
发明人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Shoichi Kawamura , Michael Shingche Chung , Vincent C. Leung , Masaru Yano
IPC分类号： G11C16/06 , G11C8/08 , G11C16/12 , G11C13/00
CPC分类号： G11C16/12 , G11C8/08
摘要： Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply. By setting the decode input at zero volts, the voltages at the gates of the boost transistors and of the pass transistor are held at zero volts, thus disabling them. In the preferred embodiment, both the regulation transistors and the discharge transistors are included in the high voltage pass gate.
摘要翻译：两个NMOS升压晶体管的源极连接到高压输入端，而它们的漏极和栅极交叉连接。两个耦合电容器将两个交替相位时钟连接到两个交叉连接的升压晶体管的栅极。 NMOS传输晶体管的栅极连接到一个NMOS升压晶体管的漏极，其源极连接到高压输入，其漏极连接到输出。在一个实施例中，两个二极管连接的调节晶体管将升压晶体管的栅极连接到高电压输入。这些连接确保升压晶体管的栅极和传输晶体管的栅极不会达到高于高电压输入以上的一个阈值电压的电压。在另一个实施例中，两个放电晶体管的漏极连接到解码输入，其源极连接到升压晶体管的栅极，并且其栅极连接到正电源。通过将解码输入设置为零伏特，升压晶体管和传输晶体管的栅极处的电压保持在零伏特，从而禁止它们。在优选实施例中，调节晶体管和放电晶体管都包括在高压通栅中。

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