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11. 发明授权

US08436651B2 Command control circuit for semiconductor integrated device 有权
标题翻译：半导体集成装置的指令控制电路
公开(公告)号：US08436651B2
公开(公告)日：2013-05-07
申请号：US12624144
申请日：2009-11-23
申请人： Hyun-Su Yoon , Jong-Chern Lee
发明人： Hyun-Su Yoon , Jong-Chern Lee
IPC分类号： G06F7/38
CPC分类号： H04L7/02 , H04L7/0045
摘要： A command control circuit of a semiconductor integrated device includes a plurality of latches sequentially connected and receiving a command signal, and a plurality of selection switches configured to pass or to interrupt the command signal inputted to each one of the plurality of latches.
摘要翻译：半导体集成装置的指令控制电路包括顺序地连接并接收命令信号的多个锁存器，以及被配置为通过或中断输入到多个锁存器中的每一个的指令信号的多个选择开关。

12. 发明授权

US08107310B2 Semiconductor memory device and method for operating the same 失效
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08107310B2
公开(公告)日：2012-01-31
申请号：US12650594
申请日：2009-12-31
申请人： Dae-Suk Kim , Jong-Chern Lee
发明人： Dae-Suk Kim , Jong-Chern Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40611 , G11C11/40618
摘要： A semiconductor memory device includes a bank having a plurality of mats, an address counting unit configured to receive an auto-refresh command consecutively applied at predetermined intervals corresponding to a number of the mats, and sequentially count an internal address in response to the auto-refresh command, and an address transferring unit configured to enable the plurality of mats in response to the auto-refresh command, and transfer the internal address to the plurality of mats at predetermined time intervals.
摘要翻译：半导体存储器件包括具有多个垫的存储体，地址计数单元，被配置为接收以对应于所述垫的数量的预定间隔连续地施加的自动刷新命令，并且响应于所述自动刷新命令顺序计数内部地址，刷新命令和地址传送单元，被配置为响应于所述自动刷新命令启用所述多个垫，并且以预定的时间间隔将所述内部地址传送到所述多个垫。

13. 发明授权

US08045400B2 Circuit and method for controlling read cycle 有权
标题翻译：用于控制读周期的电路和方法
公开(公告)号：US08045400B2
公开(公告)日：2011-10-25
申请号：US12495269
申请日：2009-06-30
申请人： Je-Yoon Kim , Jong-Chern Lee
发明人： Je-Yoon Kim , Jong-Chern Lee
IPC分类号： G11C7/00
CPC分类号： G11C19/00
摘要： A circuit for controlling the read cycle includes plurality of shift stages configured to sequentially shift read signals; and an activating unit configured to activate a read cycle signal which represents a read cycle, by performing logical operation for output signals of the plurality of the shift stages, wherein the plurality of the shift stages are configured to sequentially shift the read signals for a period corresponding to burst setting information.
摘要翻译：用于控制读周期的电路包括被配置为依次移位读信号的多个移位级; 以及激活单元，被配置为通过对所述多个移位级的输出信号执行逻辑运算来激活表示读取周期的读取周期信号，其中所述多个移位级被配置为将所读取的信号顺序地移位一段时间对应于突发设置信息。

14. 发明申请

US20080001582A1 Internal voltage generator of semiconductor device 有权
标题翻译：半导体器件的内部电压发生器
公开(公告)号：US20080001582A1
公开(公告)日：2008-01-03
申请号：US11717662
申请日：2007-03-14
申请人： Jong-Chern Lee , Sun-Hye Shin
发明人： Jong-Chern Lee , Sun-Hye Shin
IPC分类号： G05F1/10
CPC分类号： G05F1/465
摘要： An internal voltage generator of a semiconductor memory device is capable of changing driving abilities between standby and active modes, to respond faster in the active mode and prevent a leakage current in the standby mode. The internal voltage generator of a semiconductor memory device comprises a driving controller for generating drive control signals having information about standby and active modes, a first voltage generator enabled by the drive control signals for comparing an internal voltage with a reference voltage in the standby and active modes, a first driver for generating the internal voltage according to a comparison performed by the first voltage generator, a second voltage generator enabled by the drive control signal for comparing the internal voltage with the reference voltage in the active mode, and a second driver for generating the internal voltage according to a comparison performed by the second voltage generator.
摘要翻译：半导体存储器件的内部电压发生器能够改变待机模式和有源模式之间的驱动能力，以便在待机模式下更快地响应并防止在待机模式下的漏电流。半导体存储器件的内部电压发生器包括用于产生具有关于待机和有功模式的信息的驱动控制信号的驱动控制器，通过用于将内部电压与待机和有效模式下的参考电压进行比较的驱动控制信号使能的第一电压发生器模式，用于根据由第一电压发生器进行的比较产生内部电压的第一驱动器，通过用于将内部电压与活动模式中的参考电压进行比较的驱动控制信号使能的第二电压发生器和用于根据由第二电压发生器执行的比较产生内部电压。

15. 发明授权

US07157893B2 Temperature independent reference voltage generator 有权
标题翻译：温度独立参考电压发生器
公开(公告)号：US07157893B2
公开(公告)日：2007-01-02
申请号：US10878568
申请日：2004-06-29
申请人： Jong-Chern Lee
发明人： Jong-Chern Lee
IPC分类号： G05F3/16
CPC分类号： G05F3/245 , Y10S323/907
摘要： There is provided a reference voltage generator that generates a constant reference voltage regardless of a change in temperature. The reference voltage generator includes a temperature-compensated current generating part for reducing a supply current provided to an output terminal in response to an increase of temperature, and a diode for receiving the supply current through the output terminal.
摘要翻译：提供了参考电压发生器，其产生恒定的参考电压，而与温度的变化无关。参考电压发生器包括温度补偿电流产生部件，用于响应于温度升高而减小提供给输出端子的电源电流;以及二极管，用于接收通过输出端子的电源电流。

16. 发明授权

US08446197B2 Delay locked loop and method for driving the same 有权
标题翻译：延迟锁定环和驱动方法
公开(公告)号：US08446197B2
公开(公告)日：2013-05-21
申请号：US12755949
申请日：2010-04-07
申请人： Seung-Joon Ahn , Jong-Chern Lee
发明人： Seung-Joon Ahn , Jong-Chern Lee
IPC分类号： H03L7/00
CPC分类号： H03L7/0814 , H03L7/07
摘要： A delay locked loop includes a delay pulse generation unit, a coding unit, and a delay line. The delay pulse generation unit is configured to generate a delay pulse having a certain width. The coding unit is configured to code the delay pulse and output a code value. The delay line is configured to delay an input clock by the code value, and generate a delayed locked clock. The delay pulse has a logic high level state during a third period equivalent to a difference between a first period, which corresponds to an integer multiple of the input clock, and a second period, which is a certain replica delay period.
摘要翻译：延迟锁定环包括延迟脉冲产生单元，编码单元和延迟线。延迟脉冲产生单元被配置为产生具有一定宽度的延迟脉冲。编码单元被配置为对延迟脉冲进行编码并输出代码值。延迟线被配置为通过代码值来延迟输入时钟，并产生延迟的锁定时钟。延迟脉冲在与第一周期（对应于输入时钟的整数倍）和第二周期（在某个复制延迟周期）之间的差值的第三周期内具有逻辑高电平状态。

17. 发明申请

US20120249229A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME 有权
标题翻译：半导体集成电路和半导体系统，包括它们
公开(公告)号：US20120249229A1
公开(公告)日：2012-10-04
申请号：US13236970
申请日：2011-09-20
申请人： Jae-Bum KO , Jong-Chern Lee , Sang-Jin Byeon
发明人： Jae-Bum KO , Jong-Chern Lee , Sang-Jin Byeon
IPC分类号： H01L25/00
CPC分类号： G11C8/12
摘要： A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips.
摘要翻译：半导体集成电路包括分别响应于多个芯片选择信号选择的多个半导体芯片，以及芯片选择信号发生器，被配置为响应于用于决定是否驱动半导体芯片的一个第一控制信号产生芯片选择信号以及用于从半导体芯片中选择至少一个半导体芯片的至少一个第二控制信号。

18. 发明授权

US08242822B2 Delay locked loop 失效
公开(公告)号：US08242822B2
公开(公告)日：2012-08-14
申请号：US13400967
申请日：2012-02-21
申请人： Seung-Joon Ahn , Jong-Chern Lee
发明人： Seung-Joon Ahn , Jong-Chern Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0816 , H03L7/0814
摘要： A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.

19. 发明授权

US08233339B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08233339B2
公开(公告)日：2012-07-31
申请号：US12875803
申请日：2010-09-03
申请人： Hyun-Su Yoon , Jong-Chern Lee , Seung-Joon Ahn
发明人： Hyun-Su Yoon , Jong-Chern Lee , Seung-Joon Ahn
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C2207/2272
摘要： A semiconductor memory device includes an open-loop-type delay locked loop (DLL) configured to generate a clock signal locked by reflecting a first delay amount which actually occurs in a data path and a second delay amount which is required for locking the clock signal, a latency control unit configured to shift an inputted command according to a latency code value corresponding to the first delay amount and latency information, and output the shifted command, and an additional delay line configured to delay the shifted command according to a delay code value corresponding to the second delay amount, and output the command of which operation timing is controlled.
摘要翻译：半导体存储器件包括开环型延迟锁定环（DLL），其被配置为通过反映实际发生在数据路径中的第一延迟量和锁定时钟信号所需的第二延迟量来产生锁定的时钟信号等待时间控制单元，被配置为根据与第一延迟量和等待时间信息相对应的等待时间码值来移位输入的命令，并输出移位的命令;以及附加延迟线，被配置为根据延迟代码值来延迟移位的命令对应于第二延迟量，并且输出控制哪个操作定时的命令。

20. 发明申请

US20120051113A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20120051113A1
公开(公告)日：2012-03-01
申请号：US12945120
申请日：2010-11-12
申请人： Min-Seok CHOI , Jong-Chern Lee
发明人： Min-Seok CHOI , Jong-Chern Lee
IPC分类号： G11C5/02 , G11C5/06 , H01L21/50
CPC分类号： H01L25/0657 , G11C5/025 , G11C5/04 , G11C5/063 , G11C29/12 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , H01L2924/1434 , H01L2924/00
摘要： A semiconductor integrated circuit includes a plurality of slave chips each including a core area including a memory cell array, a global data line configured to transfer input/output data of the corresponding core area, and a first peripheral circuit area configured to interface the corresponding core area and the corresponding global data line, a plurality of data transfer through-chip vias vertically formed through the plurality of slave chips, respectively, and coupled to the respective global data lines of the slave chips, and a master chip including a second peripheral circuit area configured to provide an input/output interface between the data transfer through-chip vias and an external controller.
摘要翻译：半导体集成电路包括多个从芯片，每个从芯片包括包括存储单元阵列的核心区域，被配置为传送相应核心区域的输入/输出数据的全局数据线以及被配置为将对应的核心区域和对应的全局数据线，分别通过多个从芯片垂直形成并耦合到从芯片的相应全局数据线的多个数据传输通过芯片通孔，以及包括第二外围电路的主芯片区域被配置为在数据传送片上通孔和外部控制器之间提供输入/输出接口。

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