专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07187220B1 Memory clock slowdown 有权
标题翻译：内存时钟减速
公开(公告)号：US07187220B1
公开(公告)日：2007-03-06
申请号：US10741149
申请日：2003-12-18
申请人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
发明人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
IPC分类号： H03L7/06
CPC分类号： H03L7/06
摘要： Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.
摘要翻译：用于减慢图形处理器集成电路上的时钟电路的电路，方法和装置，以减少功耗。本发明的示例性实施例提供了具有两个存储器时钟，特别是开关存储器时钟和未切换存储器时钟的图形处理器。切换存储器时钟频率在特定条件下降低，而未切换的存储器时钟频率保持固定。在具体实施例中，当相关图形，显示，缩放器和帧缓冲器电路不请求数据时，切换存储器时钟频率降低，或者可以延迟这种数据请求。本发明的进一步改进提供了用于确保切换和未切换的存储器时钟信号保持同相并且彼此对准的电路，方法和装置。

12. 发明申请

US20140032828A1 SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR COPYING DATA BETWEEN MEMORY LOCATIONS 有权
标题翻译：用于复制记忆位置之间数据的系统，方法和计算机程序产品
公开(公告)号：US20140032828A1
公开(公告)日：2014-01-30
申请号：US13560315
申请日：2012-07-27
申请人： Brucek Kurdo Khailany , Sean Jeffrey Treichler
发明人： Brucek Kurdo Khailany , Sean Jeffrey Treichler
IPC分类号： G06F12/02
CPC分类号： G06F3/065 , G06F9/3004 , G06F9/30087 , G06F9/3851
摘要： A system, method, and computer program product are provided for copying data between memory locations. In use, a memory copy instruction is implemented. Additionally, data is copied from a first memory location to a second memory location, utilizing the memory copy instruction.
摘要翻译：提供了一种用于在存储器位置之间复制数据的系统，方法和计算机程序产品。在使用中，实现了存储器复制指令。此外，利用存储器复制指令，将数据从第一存储器位置复制到第二存储器位置。

13. 发明授权

US08249819B1 Virtual binning 有权
标题翻译：虚拟合并
公开(公告)号：US08249819B1
公开(公告)日：2012-08-21
申请号：US11612835
申请日：2006-12-19
申请人： Sean Jeffrey Treichler , Brian M. Kelleher
发明人： Sean Jeffrey Treichler , Brian M. Kelleher
IPC分类号： G01R15/00
CPC分类号： G01R31/31718 , G01R31/3004
摘要： An electronic device is assigned to a virtual bin by setting an operating voltage of the electronic device to a first voltage, determining an operating frequency and an operating power consumption level for the electronic device, determining an operating frequency differential equal to the absolute value of difference between the operating frequency and a minimum operating frequency of the physical bin, determining a power consumption level differential equal to the absolute value of difference between the operating power consumption level and a maximum operating power consumption level of the physical bin, and assigning a virtual bin identifier to the electronic device to identify the operating voltage of the electronic device if the operating frequency is greater than or equal to the minimum operating frequency of the physical bin and the operating power consumption level is less than or equal to the maximum power consumption level of the physical bin.
摘要翻译：通过将电子设备的工作电压设置为第一电压，确定电子设备的工作频率和操作功耗水平，将电子设备分配给虚拟箱，确定等于差分绝对值的工作频率差在所述操作频率和所述物理仓的最小工作频率之间，确定等于所述操作功率消耗水平与所述物理仓的最大操作功率消耗水平之间的差的绝对值的功率消耗水平差，以及分配虚拟箱如果操作频率大于或等于物理箱的最小工作频率，并且操作功率消耗水平小于或等于最大功率消耗水平，则识别电子设备的标识符以识别电子设备的工作电压物理仓。

14. 发明授权

US07746349B1 Method and apparatus for display of data 有权
标题翻译：用于显示数据的方法和装置
公开(公告)号：US07746349B1
公开(公告)日：2010-06-29
申请号：US11083695
申请日：2005-03-16
申请人： Krishnaraj S. Rao , David G. Reed , Sean Jeffrey Treichler
发明人： Krishnaraj S. Rao , David G. Reed , Sean Jeffrey Treichler
IPC分类号： G06T1/60 , G09G5/39 , G06F13/28
CPC分类号： G09G5/222 , G06T1/20 , G09G2360/125
摘要： To display a row of characters in the VGA alphanumeric mode, the ASCII and attribute bits for all such characters are retrieved from the main memory and stored in a local cache memory. The font and unused bits that are also retrieved from the memory during the retrieval of ASCII and attribute bits are discarded. The stored ASCII and attribute bits for each such character is then used to compute the address of the associated font bits in the main memory. Next, for each character, the font bits are retrieved from the main memory using a burst read operation and using the computed address for that font. The font bits associated with all the characters in the row are stored in the local cache memory and are subsequently scanned out to be used in the display of the characters.
摘要翻译：要以VGA字母数字模式显示一行字符，所有这些字符的ASCII和属性位将从主存储器中检索并存储在本地缓存中。在检索ASCII和属性位期间也从存储器检索的字体和未使用的位将被丢弃。每个这样的字符的存储的ASCII和属性位然后用于计算主存储器中相关字体位的地址。接下来，对于每个字符，使用突发读取操作从主存储器中检索字体位，并使用所计算的该字体的地址。与行中的所有字符相关联的字体位存储在本地高速缓冲存储器中，随后被扫描以用于字符显示。

15. 发明授权

US07042263B1 Memory clock slowdown synthesis circuit 有权
标题翻译：内存时钟减速合成电路
公开(公告)号：US07042263B1
公开(公告)日：2006-05-09
申请号：US10742572
申请日：2003-12-18
申请人： Philip Browning Johnson , Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
发明人： Philip Browning Johnson , Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
IPC分类号： H03K3/356
CPC分类号： G06F1/325 , G06F1/08 , G06F1/12 , G06F1/3215
摘要： Circuits, methods, and apparatus for reducing power on a graphics processor integrated circuit by generating two memory clock signals, reducing the frequency of one under certain conditions, and maintaining the frequency of the other. To reduce skew and jitter between these two memory clocks, and to ensure that they remain in phase, a synchronizer circuit is used by an exemplary embodiment of the present invention. The synchronizer circuit is also useful as a general application clock generator.
摘要翻译：通过产生两个存储器时钟信号来减少图形处理器集成电路上的功率的电路，方法和装置，在一定条件下降低一个频率，并保持另一个的频率。为了减少这两个存储器时钟之间的偏移和抖动，并且为了确保它们保持同相，本发明的示例性实施例使用同步器电路。同步器电路也可用作通用应用时钟发生器。

16. 发明授权

US08707081B2 Memory clock slowdown 有权
标题翻译：内存时钟减速
公开(公告)号：US08707081B2
公开(公告)日：2014-04-22
申请号：US12902147
申请日：2010-10-12
申请人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
发明人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
IPC分类号： G06F1/32
CPC分类号： H03L7/06
摘要： Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.
摘要翻译：用于减慢图形处理器集成电路上的时钟电路的电路，方法和装置，以减少功耗。本发明的示例性实施例提供了具有两个存储器时钟，特别是开关存储器时钟和未切换存储器时钟的图形处理器。切换存储器时钟频率在特定条件下降低，而未切换的存储器时钟频率保持固定。在具体实施例中，当相关图形，显示，缩放器和帧缓冲器电路不请求数据时，切换存储器时钟频率降低，或者可以延迟这种数据请求。本发明的进一步改进提供了用于确保切换和未切换的存储器时钟信号保持同相并且彼此对准的电路，方法和装置。

17. 发明授权

US07836318B1 Memory clock slowdown 有权
标题翻译：内存时钟减速
公开(公告)号：US07836318B1
公开(公告)日：2010-11-16
申请号：US11561666
申请日：2006-11-20
申请人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
发明人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
IPC分类号： G06F1/32
CPC分类号： H03L7/06
摘要： Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.
摘要翻译：用于减慢图形处理器集成电路上的时钟电路的电路，方法和装置，以减少功耗。本发明的示例性实施例提供了具有两个存储器时钟，特别是开关存储器时钟和未切换存储器时钟的图形处理器。切换存储器时钟频率在特定条件下降低，而未切换的存储器时钟频率保持固定。在具体实施例中，当相关图形，显示，缩放器和帧缓冲器电路不请求数据时，切换存储器时钟频率降低，或者可以延迟这种数据请求。本发明的进一步改进提供了用于确保切换和未切换的存储器时钟信号保持同相并且彼此对准的电路，方法和装置。

18. 发明授权

US07584321B1 Memory address and datapath multiplexing 有权
标题翻译：内存地址和数据路径复用
公开(公告)号：US07584321B1
公开(公告)日：2009-09-01
申请号：US10706056
申请日：2003-11-12
申请人： Chris Alan Malachowsky , David G. Reed , Sean Jeffrey Treichler , Brad W. Simeral
发明人： Chris Alan Malachowsky , David G. Reed , Sean Jeffrey Treichler , Brad W. Simeral
IPC分类号： G06F12/00 , G09G5/39
CPC分类号： G09G5/363 , G06F13/1684 , G09G5/393 , G09G5/395 , G09G2320/0252 , G09G2360/18
摘要： Circuits, methods, and apparatus for multiplexing addresses and data at a memory interface such that multiple data widths are provided without the need to change a motherboard or other printed circuit board design. A specific embodiment of the present invention achieves this using a single integrated circuit design where the datapath width is selected using a bonding option, fuse, data input, or other selection mechanism. The specific embodiment supports both 64 and 128-bit datapaths, though other numbers of datapaths, and other datapath widths are supported by other embodiments.
摘要翻译：用于在存储器接口处复用地址和数据的电路，方法和装置，使得提供多个数据宽度而不需要改变主板或其它印刷电路板设计。本发明的具体实施方式使用单个集成电路设计来实现，其中使用接合选项，熔丝，数据输入或其他选择机制来选择数据路径宽度。该具体实施例支持64和128位数据通路，尽管其他数据路径和其他数据路径宽度由其他实施例支持。

19. 发明授权

US07275143B1 System, apparatus and method for avoiding page conflicts by characterizing addresses in parallel with translations of memory addresses 有权
标题翻译：用于通过与存储器地址的转换并行表征地址来避免页面冲突的系统，装置和方法
公开(公告)号：US07275143B1
公开(公告)日：2007-09-25
申请号：US11012007
申请日：2004-12-13
申请人： Brad W. Simeral , Sean Jeffrey Treichler , David G. Reed
发明人： Brad W. Simeral , Sean Jeffrey Treichler , David G. Reed
IPC分类号： G06F12/00 , G06F9/26 , G06F9/34 , G06F12/06 , G06F21/00
CPC分类号： G06F21/79 , G06F12/0292 , G06F12/0607
摘要： A system, apparatus, and method are disclosed for controlling accesses into memory to minimize sequential accesses to the same bank of memory, at least in part, by characterizing a subset of an address in parallel with address translations associated with those accesses. In one embodiment, an exemplary memory controller can include an address translator configured to translate an address useable by a processor to a first memory address. Also, the memory controller includes a bit characterizer configured to characterize a subset of the address as having a value from a range of values, and a bank separator coupled to the address translator and the bit characterizer for receiving a first portion of the first memory address and the value, respectively. Accordingly, the bank separator is configured to differentiate the first portion from a second portion of a second memory address.
摘要翻译：公开了一种系统，装置和方法，用于至少部分地通过与与这些访问相关联的地址转换并行地表征地址的子集来控制对存储器的访问以最小化对同一存储体的顺序访问。在一个实施例中，示例性存储器控制器可以包括地址转换器，其被配置为将处理器可使用的地址转换为第一存储器地址。此外，存储器控制器包括位表示器，其被配置为将地址的子集表征为具有来自值范围的值，以及耦合到地址转换器和位表征器的存储体分离器，用于接收第一存储器地址的第一部分和值。因此，银行分隔符被配置为将第一部分与第二存储器地址的第二部分区分开。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式