专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07042263B1 Memory clock slowdown synthesis circuit 有权
标题翻译：内存时钟减速合成电路
公开(公告)号：US07042263B1
公开(公告)日：2006-05-09
申请号：US10742572
申请日：2003-12-18
申请人： Philip Browning Johnson , Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
发明人： Philip Browning Johnson , Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
IPC分类号： H03K3/356
CPC分类号： G06F1/325 , G06F1/08 , G06F1/12 , G06F1/3215
摘要： Circuits, methods, and apparatus for reducing power on a graphics processor integrated circuit by generating two memory clock signals, reducing the frequency of one under certain conditions, and maintaining the frequency of the other. To reduce skew and jitter between these two memory clocks, and to ensure that they remain in phase, a synchronizer circuit is used by an exemplary embodiment of the present invention. The synchronizer circuit is also useful as a general application clock generator.
摘要翻译：通过产生两个存储器时钟信号来减少图形处理器集成电路上的功率的电路，方法和装置，在一定条件下降低一个频率，并保持另一个的频率。为了减少这两个存储器时钟之间的偏移和抖动，并且为了确保它们保持同相，本发明的示例性实施例使用同步器电路。同步器电路也可用作通用应用时钟发生器。

2. 发明申请

US20110191615A1 MEMORY CLOCK SLOWDOWN 有权
标题翻译：内存时钟缓存
公开(公告)号：US20110191615A1
公开(公告)日：2011-08-04
申请号：US12902147
申请日：2010-10-12
申请人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
发明人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
IPC分类号： G06F1/32 , G06F1/12 , G06T1/00 , G06F13/14
CPC分类号： H03L7/06
摘要： Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.
摘要翻译：用于减慢图形处理器集成电路上的时钟电路的电路，方法和装置，以减少功耗。本发明的示例性实施例提供了具有两个存储器时钟，特别是开关存储器时钟和未切换存储器时钟的图形处理器。切换存储器时钟频率在特定条件下降低，而未切换的存储器时钟频率保持固定。在具体实施例中，当相关图形，显示，缩放器和帧缓冲器电路不请求数据时，切换存储器时钟频率降低，或者可以延迟这种数据请求。本发明的进一步改进提供了用于确保切换和未切换的存储器时钟信号保持同相并且彼此对准的电路，方法和装置。

3. 发明授权

US07187220B1 Memory clock slowdown 有权
标题翻译：内存时钟减速
公开(公告)号：US07187220B1
公开(公告)日：2007-03-06
申请号：US10741149
申请日：2003-12-18
申请人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
发明人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
IPC分类号： H03L7/06
CPC分类号： H03L7/06
摘要： Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.
摘要翻译：用于减慢图形处理器集成电路上的时钟电路的电路，方法和装置，以减少功耗。本发明的示例性实施例提供了具有两个存储器时钟，特别是开关存储器时钟和未切换存储器时钟的图形处理器。切换存储器时钟频率在特定条件下降低，而未切换的存储器时钟频率保持固定。在具体实施例中，当相关图形，显示，缩放器和帧缓冲器电路不请求数据时，切换存储器时钟频率降低，或者可以延迟这种数据请求。本发明的进一步改进提供了用于确保切换和未切换的存储器时钟信号保持同相并且彼此对准的电路，方法和装置。

4. 发明授权

US08707081B2 Memory clock slowdown 有权
标题翻译：内存时钟减速
公开(公告)号：US08707081B2
公开(公告)日：2014-04-22
申请号：US12902147
申请日：2010-10-12
申请人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
发明人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
IPC分类号： G06F1/32
CPC分类号： H03L7/06
摘要： Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.
摘要翻译：用于减慢图形处理器集成电路上的时钟电路的电路，方法和装置，以减少功耗。本发明的示例性实施例提供了具有两个存储器时钟，特别是开关存储器时钟和未切换存储器时钟的图形处理器。切换存储器时钟频率在特定条件下降低，而未切换的存储器时钟频率保持固定。在具体实施例中，当相关图形，显示，缩放器和帧缓冲器电路不请求数据时，切换存储器时钟频率降低，或者可以延迟这种数据请求。本发明的进一步改进提供了用于确保切换和未切换的存储器时钟信号保持同相并且彼此对准的电路，方法和装置。

5. 发明授权

US07836318B1 Memory clock slowdown 有权
标题翻译：内存时钟减速
公开(公告)号：US07836318B1
公开(公告)日：2010-11-16
申请号：US11561666
申请日：2006-11-20
申请人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
发明人： Jonah M. Alben , Sean Jeffrey Treichler , Adam E. Levinthal
IPC分类号： G06F1/32
CPC分类号： H03L7/06
摘要： Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides a graphics processor having two memory clocks, specifically, a switched memory clock and an unswitched memory clock. The switched memory clock frequency is reduced under specific conditions, while the unswitched memory clock frequency remains fixed. In a specific embodiment, the switched memory clock frequency is reduced when related graphics, display, scaler, and frame buffer circuits are not requesting data, or are such data requests can be delayed. Further refinements to the present invention provide circuits, methods, and apparatus for ensuring that the switched and unswitched memory clock signals remain in-phase and aligned with each other.
摘要翻译：用于减慢图形处理器集成电路上的时钟电路的电路，方法和装置，以减少功耗。本发明的示例性实施例提供了具有两个存储器时钟，特别是开关存储器时钟和未切换存储器时钟的图形处理器。切换存储器时钟频率在特定条件下降低，而未切换的存储器时钟频率保持固定。在具体实施例中，当相关图形，显示，缩放器和帧缓冲器电路不请求数据时，切换存储器时钟频率降低，或者可以延迟这种数据请求。本发明的进一步改进提供了用于确保切换和未切换的存储器时钟信号保持同相并且彼此对准的电路，方法和装置。

6. 发明授权

US5643086A Electronic casino gaming apparatus with improved play capacity, authentication and security 失效
标题翻译：具有改善游戏容量，认证和安全性的电子赌场游戏机
公开(公告)号：US5643086A
公开(公告)日：1997-07-01
申请号：US497662
申请日：1995-06-29
申请人： Allan E. Alcorn , Michael Barnett , Louis D. Giacalone, Jr. , Adam E. Levinthal
发明人： Allan E. Alcorn , Michael Barnett , Louis D. Giacalone, Jr. , Adam E. Levinthal
IPC分类号： A63F13/00 , G06F1/00 , G06F19/00 , G06F21/00 , G06Q50/34 , G07F17/32 , H04L9/32 , A63F9/24
CPC分类号： G06F21/00 , G06F21/51 , G06F21/57 , G06F21/64 , G06Q50/34 , G07F17/32 , G07F17/3288 , H04L9/3236 , H04L9/3247 , G06F2211/007 , G06F2221/2109 , H04L2209/60
摘要： An electronic casino gaming system includes an unalterable ROM for storing a casino game authentication program, including a message digest algorithm program, a decryption program and a decryption key. A casino game data set containing casino game rules and image data is stored in a mass storage device, such as a local disk memory or a remote network file server, along with the signature of the casino game data set. The signature is an encrypted version of the message digest of the casino game data set, prepared using a hash function. Prior to permitting game play by a player, the casino game data set is transferred from the mass storage device to main memory and during this process the message digest is computed from the image data using a hash function stored in the ROM. The encrypted version of the message digest transferred from the mass storage device is decrypted using the decryption program and decryption key stored in the unalterable ROM. The two message digests are then compared for a match: if a match exists, game play is permitted; if a match does not exist, game play is prohibited. The authentication procedure is also used to check all casino game software, both programs and fixed data sets, stored in any memory devices distributed throughout the system, such as the system boot ROM, NVRAM and all sub-system memory devices. The authentication procedure is run whenever a particular program or fixed data set is scheduled for use by the system, and also at periodic intervals and on demand.
摘要翻译：电子赌场游戏系统包括用于存储娱乐场游戏认证程序的不可变更ROM，包括消息摘要算法程序，解密程序和解密密钥。包含娱乐场游戏规则和图像数据的娱乐场游戏数据集与娱乐场游戏数据集的签名一起存储在诸如本地磁盘存储器或远程网络文件服务器的大容量存储设备中。签名是使用散列函数准备的娱乐场游戏数据集的消息摘要的加密版本。在允许玩家玩游戏之前，赌场游戏数据集从大容量存储装置传送到主存储器，并且在该处理期间，使用存储在ROM中的散列函数从图像数据计算消息摘要。从大容量存储设备传送的消息摘要的加密版本使用存储在不可更改ROM中的解密程序和解密密钥进行解密。然后将两个消息摘要进行比较：如果匹配存在，则允许游戏; 如果比赛不存在，禁止玩游戏。验证过程还用于检查存储在整个系统中的任何存储设备中的所有娱乐场游戏软件，包括程序和固定数据集，例如系统引导ROM，NVRAM和所有子系统存储器设备。只要某个特定的程序或固定数据集被安排供系统使用，并且按照周期性的间隔和按需，就会运行身份验证过程。

7. 再颁专利

USRE39400E1 Electronic casino gaming system with improved play capacity, authentication and security 失效
公开(公告)号：USRE39400E1
公开(公告)日：2006-11-14
申请号：US10225116
申请日：1996-06-17
申请人： Allan E. Alcorn , Michael Barnett , Louis D. Giacalone, Jr. , Adam E. Levinthal
发明人： Allan E. Alcorn , Michael Barnett , Louis D. Giacalone, Jr. , Adam E. Levinthal
IPC分类号： A63F13/00 , G06F5/00
摘要： The electronic casino gaming system consists of several system components, including a microprocessor (12), a main memory unit (13) that is typically a random access memory, and a system boot ROM (14). Also included in the electronic casino gaming system are a non-volatile RAM (17), a mass storage unit (18), a disk subsystem (19), and a PCI bus (20). The disk subsystem (19) preferably supports SCSI-2 with options of fast and wide. A video subsystem (22) is also included in the electronic casino gaming system and is coupled to the PCI bus (20) to provide full color still images and MPEG movies.

8. 发明授权

US07369132B1 Apparatus, system, and method for delivering data to multiple memory clients via a unitary buffer 有权
标题翻译：用于通过单一缓冲器将数据传送到多个存储器客户端的装置，系统和方法
公开(公告)号：US07369132B1
公开(公告)日：2008-05-06
申请号：US11688703
申请日：2007-03-20
申请人： Brijesh Tripathi , Wayne Douglas Young , Adam E. Levinthal , Stephen M. Ryan
发明人： Brijesh Tripathi , Wayne Douglas Young , Adam E. Levinthal , Stephen M. Ryan
IPC分类号： G06F15/00 , G06F13/00 , G09G5/36 , G06T1/20 , G06T1/00 , G06T15/00 , G06F15/167 , G06F13/28
CPC分类号： G06T1/60 , G06F13/4059 , G09G5/363
摘要： A graphics processing apparatus includes an output pipeline including a set of memory clients. The graphics processing apparatus also includes a memory controller connected to the output pipeline. The memory controller is configured to retrieve data requested by respective ones of the memory clients from a memory. The graphics processing apparatus further includes a buffering module connected between the memory controller and the output pipeline. The buffering module includes a buffer including a buffering space shared by the memory clients. The buffering module also includes a buffer controller connected to the buffer. The buffer controller is configured to: (1) dynamically assign portions of the buffering space to respective ones of the memory clients; (2) coordinate storage of the data in the assigned portions; and (3) coordinate delivery of the data from the assigned portions to respective ones of the memory clients.
摘要翻译：图形处理装置包括包括一组存储器客户端的输出管线。图形处理装置还包括连接到输出管线的存储器控制器。存储器控制器被配置为从存储器检索由相应的存储器客户端请求的数据。图形处理装置还包括连接在存储器控制器和输出管线之间的缓冲模块。缓冲模块包括缓冲器，该缓冲器包括存储器客户机共享的缓冲空间。缓冲模块还包括连接到缓冲器的缓冲器控制器。所述缓冲器控制器被配置为：（1）将所述缓冲空间的部分动态分配给所述存储器客户端中的相应存储器; （2）在分配的部分中协调数据的存储; 和（3）将数据从分配的部分协调到相应的存储器客户端。

9. 再颁专利

USRE39401E1 Electronic casino gaming system with improved play capacity, authentication and security 失效
公开(公告)号：USRE39401E1
公开(公告)日：2006-11-14
申请号：US10225096
申请日：1996-06-17
申请人： Allan E. Alcorn , Michael Barnett , Louis D. Giacalone, Jr. , Adam E. Levinthal
发明人： Allan E. Alcorn , Michael Barnett , Louis D. Giacalone, Jr. , Adam E. Levinthal
IPC分类号： A63F13/00 , G06F5/00
摘要： The electronic casino gaming system consists of several system components, including a microprocessor (12), a main memory unit (13) that is typically a random access memory, and a system boot ROM (14). Also included in the electronic casino gaming system are a non-volatile RAM (17), a mass storage unit (18), a disk subsystem (19), and a PCI bus (20). The disk subsystem (19) preferably supports SCSI-2 with options of fast and wide. A video subsystem (22) is also included in the electronic casino gaming system and is coupled to the PCI bus (20) to provide full color still images and MPEG movies.

10. 发明授权

US5045995A Selective operation of processing elements in a single instruction multiple data stream (SIMD) computer system 失效
标题翻译：单指令多数据流（SIMD）计算机系统中处理元素的选择性操作
公开(公告)号：US5045995A
公开(公告)日：1991-09-03
申请号：US622229
申请日：1990-12-03
申请人： Adam E. Levinthal , Thomas K. Porter , Thomas D. S. Duff , Loren C. Carpenter
发明人： Adam E. Levinthal , Thomas K. Porter , Thomas D. S. Duff , Loren C. Carpenter
IPC分类号： G06F15/80
CPC分类号： G06F9/3885 , G06F15/8007 , G06F9/3842 , G06F9/3887
摘要： A plurality of processing elements independently operate in parallel on separate streams of data but in response to common instructions. In order to selectively and individually enable each processing element, a control register stage is provided for each. Each register may be controlled, as between its enabling and disabling states with respect to execution of a common instruction, by the results of a test performed by its associated processor in response to a prior instruction and by the complement of the test results. The system is especially adapted to support flow of control operators, such as IF/THEN constructs, IF/THEN/ELSE constructs and WHILE/DO loop constructs.
摘要翻译：多个处理元件独立地在单独的数据流上并行操作，而是响应于共同的指令。为了选择性地和单独地启用每个处理元件，为每个处理元件提供控制寄存器级。通过响应于先前的指令和测试结果的补充，其相关联的处理器进行的测试的结果，可以控制每个寄存器，就其相对于公共指令的执行而言在其启用和禁用状态之间。该系统特别适用于支持诸如IF / THEN结构，IF / THEN / ELSE结构和WHILE / DO循环结构等控制运算符的流程。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式