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11. 发明申请

US20120126339A1 SEMICONDUCTOR TRANSISTORS HAVING REDUCED DISTANCES BETWEEN GATE ELECTRODE REGIONS 有权
标题翻译：栅极电极区域之间具有减少的距离的半导体晶体管
公开(公告)号：US20120126339A1
公开(公告)日：2012-05-24
申请号：US13357757
申请日：2012-01-25
申请人： Robert C. Wong , Haining S. Yang
发明人： Robert C. Wong , Haining S. Yang
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/823437 , H01L21/823475 , H01L27/0207 , Y10S257/903
摘要： A semiconductor structure. The semiconductor structure includes: a semiconductor substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface and further includes a first semiconductor body region and a second semiconductor body region; a first gate dielectric region and a second gate dielectric region on top of the first and second semiconductor body regions, respectively; a first gate electrode region on top of the semiconductor substrate and the first gate dielectric region; a second gate electrode region on top of the semiconductor substrate and the second gate dielectric region; and a gate divider region in direct physical contact with the first and second gate electrode regions. The gate divider region does not overlap the first and second gate electrode regions in the reference direction.
摘要翻译：半导体结构。半导体结构包括：半导体衬底，其包括限定垂直于顶部衬底表面的参考方向的顶部衬底表面，并且还包括第一半导体本体区域和第二半导体本体区域; 分别在第一和第二半导体本体区域的顶部上的第一栅极电介质区域和第二栅极电介质区域; 在所述半导体衬底和所述第一栅极电介质区域的顶部上的第一栅极电极区域; 在所述半导体衬底和所述第二栅极电介质区域的顶部上的第二栅极电极区域; 以及与第一和第二栅电极区域直接物理接触的栅极分压区域。栅极分压器区域在参考方向上不与第一和第二栅电极区域重叠。

12. 发明授权

US08159031B2 SOI substrates and SOI devices, and methods for forming the same 有权
标题翻译： SOI衬底和SOI器件及其形成方法
公开(公告)号：US08159031B2
公开(公告)日：2012-04-17
申请号：US12709873
申请日：2010-02-22
申请人： Thomas W. Dyer , Zhijiong Luo , Haining S. Yang
发明人： Thomas W. Dyer , Zhijiong Luo , Haining S. Yang
IPC分类号： H01L27/12
CPC分类号： H01L29/0653 , H01L21/76243 , H01L21/76267 , H01L21/76283 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： An improved semiconductor-on-insulator (SOI) substrate is provided, which contains a patterned buried insulator layer at varying depths. Specifically, the SOI substrate has a substantially planar upper surface and comprises: (1) first regions that do not contain any buried insulator, (2) second regions that contain first portions of the patterned buried insulator layer at a first depth (i.e., measured from the planar upper surface of the SOI substrate), and (3) third regions that contain second portions of the patterned buried insulator layer at a second depth, where the first depth is larger than the second depth. One or more field effect transistors (FETs) can be formed in the SOI substrate. For example, the FETs may comprise: channel regions in the first regions of the SOI substrate, source and drain regions in the second regions of the SOI substrate, and source/drain extension regions in the third regions of the SOI substrate.
摘要翻译：提供了一种改进的绝缘体上半导体（SOI）衬底，其包含在不同深度处的图案化掩埋绝缘体层。具体而言，SOI衬底具有基本平坦的上表面，并且包括：（1）不包含任何埋入绝缘体的第一区域，（2）第一区域，其包含第一深度处的图案化掩埋绝缘体层的第一部分从SOI衬底的平坦的上表面），和（3）第二深度大于第二深度的第二深度上包含图案化的掩埋绝缘体层的第二部分的第三区域。可以在SOI衬底中形成一个或多个场效应晶体管（FET）。例如，FET可以包括：SOI衬底的第一区域中的沟道区域，SOI衬底的第二区域中的源极和漏极区域以及SOI衬底的第三区域中的源极/漏极延伸区域。

13. 发明申请

US20110175170A1 STRUCTURE AND METHOD FOR MAKING LOW LEAKAGE AND LOW MISMATCH NMOSFET 失效
标题翻译：用于制造低漏电和低失真的NMOSFET的结构和方法
公开(公告)号：US20110175170A1
公开(公告)日：2011-07-21
申请号：US12691183
申请日：2010-01-21
申请人： Xinlin Wang , Xiangdong Chen , Haining S. Yang
发明人： Xinlin Wang , Xiangdong Chen , Haining S. Yang
IPC分类号： H01L29/66 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/823462 , H01L21/823468 , H01L21/823857 , H01L21/823864 , H01L27/11 , H01L27/1104
摘要： An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation, GIDL and junction leakage.
摘要翻译：公开了一种改进的SRAM和制造方法。该方法包括使用氮化物层来封装PFET和逻辑NFET，保护这些器件的栅极免受氧气暴露。用于SRAM单元中的NFET在退火过程中暴露于氧气，这改变了栅极金属的有效功函数，使得阈值电压增加，而不需要增加掺杂剂浓度，这可能不利地影响问题例如由于随机掺杂剂波动，GIDL和结泄漏引起的失配。

14. 发明授权

US07935993B2 Semiconductor device structure having enhanced performance FET device 有权
标题翻译：具有增强型FET器件的半导体器件结构
公开(公告)号：US07935993B2
公开(公告)日：2011-05-03
申请号：US12643482
申请日：2009-12-21
申请人： Xiangdong Chen , Haining S. Yang
发明人： Xiangdong Chen , Haining S. Yang
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate: a first layer below and second layers on a gate with spacers, source and drain regions adjacent to the gate, silicides on the gate and source and drain regions; disposing a stress layer over the structure resulting from the forming step; disposing an insulating layer over the stress layer; removing portions of the insulating layer to expose a top surface of the stress layer; removing the top surface and other portions of the stress layer and portions of the spacers to form a trench, and then disposing a suitable stress material into the trench.
摘要翻译：一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成：在栅极上的第一层和栅极上的第二层，具有间隔物，与栅极相邻的源极和漏极区域，栅极上的硅化物和源极和漏极区域; 在由成形步骤导致的结构上设置应力层; 在应力层上设置绝缘层; 去除绝缘层的部分以暴露应力层的顶表面; 去除应力层的顶表面和其它部分和间隔物的部分以形成沟槽，然后将合适的应力材料设置到沟槽中。

15. 发明授权

US07884448B2 High performance 3D FET structures, and methods for forming the same using preferential crystallographic etching 有权
标题翻译：高性能3D FET结构，以及使用优先晶体蚀刻形成相同方法
公开(公告)号：US07884448B2
公开(公告)日：2011-02-08
申请号：US12500396
申请日：2009-07-09
申请人： Thomas W. Dyer , Haining S. Yang
发明人： Thomas W. Dyer , Haining S. Yang
IPC分类号： H01L29/04
CPC分类号： H01L21/823807 , H01L21/823821 , H01L27/0922 , H01L27/1211 , H01L29/04 , H01L29/66795 , H01L29/7853
摘要： The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.
摘要翻译：本发明涉及高性能三维（3D）场效应晶体管（FET）。具体而言，可以使用具有沿着第一组等效晶面中的一个取向的底表面和沿着第二不同组的等效晶面取向的多个附加表面的3D半导体结构，以形成具有载体通道定向的高性能3D FET 沿着第二个不同组的等效晶面。更重要的是，这种3D半导体结构可以容易地在具有底表面和多个附加表面的附加3D半导体结构的同一衬底上形成，所述另外的三维半导体结构全部沿着第一组等效晶面取向。附加的3D半导体结构可以用于形成附加的3D FET，其与上述3D FET互补，并且具有沿着第一组等效晶面取向的载流子通道。

16. 发明授权

US07867832B2 Electrical fuse and method of making 有权
标题翻译：电熔丝及其制作方法
公开(公告)号：US07867832B2
公开(公告)日：2011-01-11
申请号：US12268549
申请日：2008-11-11
申请人： Chih-Chao Yang , Haining S. Yang
发明人： Chih-Chao Yang , Haining S. Yang
IPC分类号： H01L23/62
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a substrate, forming a trench feature in the substrate, depositing fuse material in the trench feature, depositing compressive stress liner material over the fuse material, and patterning the compressive stress liner material.
摘要翻译：一种半导体保险丝及其制作方法。保险丝包括熔丝元件和压缩应力衬垫，其减小了熔丝元件的电迁移电阻。该方法包括形成衬底，在衬底中形成沟槽特征，在沟槽特征中沉积熔丝材料，在熔丝材料上沉积压应力衬垫材料，以及图案化压应力衬垫材料。

17. 发明授权

US07859044B2 Partially gated FINFET with gate dielectric on only one sidewall 有权
标题翻译：部分选通FINFET，仅在一个侧壁上具有栅极电介质
公开(公告)号：US07859044B2
公开(公告)日：2010-12-28
申请号：US11782079
申请日：2007-07-24
申请人： Robert C. Wong , Haining S. Yang
发明人： Robert C. Wong , Haining S. Yang
IPC分类号： H01L29/78 , H01L27/12
CPC分类号： H01L29/66795 , H01L21/845 , H01L27/11 , H01L27/1108 , H01L27/1211 , H01L29/785
摘要： A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the opposite side of the first sidewall is not controlled by the gate electrode. A partially gated finFET, that is, a finFET with a gate electrode on the first sidewall and without a gate electrode on the second sidewall is thus formed. Conventional dual gate finFETs may be formed with the inventive partially gated finFETs on the same substrate to provide multiple finFETs having different on-current in the same circuit such as an SRAM circuit.
摘要翻译：在至少一个半导体鳍片的侧壁上形成栅极电介质和栅极导体层。图案化栅极导体层，使得栅极电极形成在半导体鳍片的一部分的第一侧壁上，而在第一侧壁的相对侧上的第二侧壁不受栅电极控制。因此，形成了部分选通的finFET，即在第一侧壁上具有栅电极且在第二侧壁上没有栅电极的finFET。传统的双栅极finFET可以在同一衬底上与本发明的部分选通的鳍状FET形成，以在诸如SRAM电路的同一电路中提供具有不同导通电流的多个finFET。

18. 发明申请

US20100295132A1 PROGRAMMABLE PN ANTI-FUSE 有权
标题翻译：可编程PN防熔丝
公开(公告)号：US20100295132A1
公开(公告)日：2010-11-25
申请号：US12698302
申请日：2010-02-02
申请人： Ping-Chuan Wang , Robert C. Wong , Haining S. Yang
发明人： Ping-Chuan Wang , Robert C. Wong , Haining S. Yang
IPC分类号： H01L27/06 , H01L21/8234 , H01L21/326
CPC分类号： H01L27/0727 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： Structure and method for providing a programmable anti-fuse in a FET structure. A method of forming the programmable anti-fuse includes: providing a p− substrate with an n+ gate stack; implanting an n+ source region and an n+ drain region in the p− substrate; forming a resist mask over the n+ drain region, while leaving the n+ source region exposed; etching the n+ source region to form a recess in the n+ source region; and growing a p+ epitaxial silicon germanium layer in the recess in the n+ source region to form a pn junction that acts as a programmable diode or anti-fuse.
摘要翻译：在FET结构中提供可编程反熔丝的结构和方法。形成可编程反熔丝的方法包括：提供具有n +栅极叠层的p衬底; 在p衬底中注入n +源极区域和n +漏极区域; 在n +漏极区域上形成抗蚀剂掩模，同时使n +源极区域露出; 蚀刻n +源极区域以在n +源极区域中形成凹陷; 以及在n +源极区的凹槽中生长p +外延硅锗层以形成用作可编程二极管或反熔丝的pn结。

19. 发明授权

US07791109B2 Metal silicide alloy local interconnect 失效
标题翻译：金属硅化物合金局部互连
公开(公告)号：US07791109B2
公开(公告)日：2010-09-07
申请号：US11693035
申请日：2007-03-29
申请人： Clement H. Wann , Haining S. Yang
发明人： Clement H. Wann , Haining S. Yang
IPC分类号： H01L27/10 , H01L27/11 , G11C5/06 , G11C11/00 , G11C11/34
CPC分类号： H01L21/76895 , G11C11/412 , H01L27/11 , H01L27/1104 , Y10S257/903
摘要： A local interconnect is formed with a gate conductor line that has an exposed sidewall on an active area of a semiconductor substrate. The exposes sidewall comprises a silicon containing material that may form a silicide alloy upon silicidation. During a silicidation process, a gate conductor sidewall silicide alloy forms on the exposed sidewall of the gate conductor line and an active area silicide is formed on the active area. The two silicides are joined to provide an electrical connection between the active area and the gate conductor line. Multiple sidewalls may be exposed on the gate conductor line to make multiple connections to different active area silicides.
摘要翻译：局部互连形成有栅极导体线，其在半导体衬底的有源区上具有暴露的侧壁。暴露的侧壁包括可以在硅化时形成硅化物合金的含硅材料。在硅化工艺期间，在栅极导体线的暴露的侧壁上形成栅极导体侧壁硅化物合金，并且在有源区上形成有源区硅化物。两个硅化物被接合以在有源区域和栅极导体线之间提供电连接。多个侧壁可能暴露在栅极导体线上，以使多个连接到不同的有源区硅化物。

20. 发明授权

US07781847B2 Device patterned with sub-lithographic features with variable widths 失效
标题翻译：用具有可变宽度的亚光刻特征构图的装置
公开(公告)号：US07781847B2
公开(公告)日：2010-08-24
申请号：US12034972
申请日：2008-02-21
申请人： Haining S. Yang
发明人： Haining S. Yang
IPC分类号： H01L27/088
CPC分类号： H01L21/0337 , H01L21/0334 , H01L21/3086 , H01L21/3088 , H01L21/76229 , H01L21/84 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L27/1203 , Y10S438/942 , Y10S438/947 , Y10S977/887
摘要： A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths and exposing sidewalls of the dummy elements and portions of the top surface of the cap layer aside from the dummy elements. Deposit a spacer layer over the device covering the patterned dummy elements and exposed surfaces of the cap layer. Etch back the spacer layer forming sidewall spacers aside from the sidewalls of the patterned dummy elements spaced above a minimum spacing and forming super-wide spacers between sidewalls of the patterned dummy elements spaced less than the minimum spacing. Strip the patterned dummy elements. Expose portions of the substrate aside from the sidewall spacers. Pattern exposed portions of the substrate by etching into the substrate.
摘要翻译：处理装置的基板的方法包括以下步骤。在基材上形成盖层。在盖层上形成虚设层，盖层具有顶表面。蚀刻虚拟层，形成具有可变宽度的图案化虚拟元件，并暴露虚拟元件的侧壁和除了虚拟元件之外的盖层的顶表面的部分。在覆盖图案化的虚拟元件和盖层的暴露表面的器件上沉积间隔层。将形成侧壁间隔物的间隔层向后蚀刻，除了图案化的虚设元件的侧壁之间间隔开最小间隔，并且在图案化的虚设元件的侧壁之间形成超宽间隔物，其间隔开小于最小间隔。剥去图案的虚拟元素。将侧衬垫的一部分露出。通过蚀刻到衬底中的衬底的图案曝光部分。

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