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11. 发明申请

US20120313177A1 Multiple Finger Structure 有权
标题翻译：多指结构
公开(公告)号：US20120313177A1
公开(公告)日：2012-12-13
申请号：US13158133
申请日：2011-06-10
申请人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou , Hung-Jen Liao
发明人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/0207 , H01L27/088 , H01L27/1104
摘要： A multiple finger structure comprises a plurality of active regions placed between a pair of dummy POLY lines. The active regions comprise a plurality of multiple fingered NMOS transistors, which are part of a sense amplifier of an SRAM memory circuit. The drain and source of each multiple fingered NMOS transistor have an SiP/SiC epitaxial growth region. The active regions extend and overlap with the dummy POLY lines. The overlap between the active regions and the dummy POLY lines helps to reduce edge imperfection at the edge of the active regions.
摘要翻译：多指结构包括放置在一对虚拟POLY线之间的多个有源区域。有源区域包括多个多指状NMOS晶体管，它们是SRAM存储器电路的读出放大器的一部分。每个多指尖的NMOS晶体管的漏极和源极具有SiP / SiC外延生长区域。有源区域与虚拟POLY线路延伸并重叠。有源区域和虚拟POLY线之间的重叠有助于减少有源区域边缘处的边缘缺陷。

12. 发明授权

US07952939B2 Circuit and method for VDD-tracking CVDD voltage supply 有权
标题翻译：用于VDD跟踪CVDD电压源的电路和方法
公开(公告)号：US07952939B2
公开(公告)日：2011-05-31
申请号：US12205243
申请日：2008-09-05
申请人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou
发明人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C5/147
摘要： Circuit and methods for providing the CVDD supply to the cells in an SRAM array while maintaining a desired VDD voltage. A circuit is described for tracking the VDD supply voltage and providing a CVDD supply for the SRAM cells that maintains an offset above VDD until a maximum voltage for the CVDD voltage is reached. The CVDD voltage supplies the word line drivers and the cells in an SRAM array, while the bit line precharge and the remaining circuitry is operated on the VDD supply. By maintaining a maximum offset between the voltage CVDD and the supply voltage VDD, the SRAM will have the required static noise margins for reliable operation, while a lowered VDD_min voltage may also be obtained. A method for supplying a CVDD voltage to an SRAM cell array is disclosed where the CVDD voltage tracks a VDD supply voltage plus a predetermined offset voltage.
摘要翻译：用于向SRAM阵列中的单元提供CVDD电源同时保持期望的VDD电压的电路和方法。描述了用于跟踪VDD电源电压并为SRAM单元提供CVDD电源的电路，其保持高于VDD的偏移，直到达到CVDD电压的最大电压。 CVDD电压为SRAM阵列中的字线驱动器和单元供电，而位线预充电和其余电路在VDD电源上工作。通过保持电压CVDD和电源电压VDD之间的最大偏移，SRAM将具有用于可靠运行的所需静态噪声容限，同时也可获得降低的VDD_min电压。公开了一种向SRAM单元阵列提供CVDD电压的方法，其中CVDD电压跟踪VDD电源电压加上预定的偏移电压。

13. 发明授权

US08767493B2 SRAM differential voltage sensing apparatus 有权
标题翻译： SRAM差分电压检测装置
公开(公告)号：US08767493B2
公开(公告)日：2014-07-01
申请号：US13169511
申请日：2011-06-27
申请人： Yen-Huei Chen , Kun-hsi Li , Shao-Yu Chou , Hung-Jen Liao , Wei Min Chan
发明人： Yen-Huei Chen , Kun-hsi Li , Shao-Yu Chou , Hung-Jen Liao , Wei Min Chan
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/062 , G11C11/419
摘要： An SRAM differential voltage sensing apparatus is coupled to a memory circuit. The memory circuit comprises a memory bank, a plurality of bit lines, a plurality of data lines coupled to the plurality of bit lines via a plurality of transmission gates and a sense amplifier. When the sense amplifier operates in a characterization mode, the transmission gates and pre-charge circuits are turned off. The differential voltage sensing apparatus applies a characterization signal to the sense amplifier and obtains the parameters of the memory circuit through a trial and error process.
摘要翻译： SRAM差分电压感测装置耦合到存储器电路。存储器电路包括存储体，多个位线，经由多个传输门和读出放大器耦合到多个位线的多条数据线。当感测放大器在表征模式下工作时，传输门和预充电电路被关断。差分电压感测装置将表征信号应用于感测放大器，并通过试错过程获得存储器电路的参数。

14. 发明授权

US08723265B2 Semiconductor structure with dummy polysilicon lines 有权
标题翻译：具有虚设多晶硅线的半导体结构
公开(公告)号：US08723265B2
公开(公告)日：2014-05-13
申请号：US13158133
申请日：2011-06-10
申请人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou , Hung-Jen Liao
发明人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： H01L21/70 , H01L27/32
CPC分类号： H01L27/0207 , H01L27/088 , H01L27/1104
摘要： A multiple finger structure comprises a plurality of active regions placed between a pair of dummy POLY lines. The active regions comprise a plurality of multiple fingered NMOS transistors, which are part of a sense amplifier of an SRAM memory circuit. The drain and source of each multiple fingered NMOS transistor have an SiP/SiC epitaxial growth region. The active regions extend and overlap with the dummy POLY lines. The overlap between the active regions and the dummy POLY lines helps to reduce edge imperfection at the edge of the active regions.
摘要翻译：多指结构包括放置在一对虚拟POLY线之间的多个有源区域。有源区域包括多个多指状NMOS晶体管，它们是SRAM存储器电路的读出放大器的一部分。每个多指尖的NMOS晶体管的漏极和源极具有SiP / SiC外延生长区域。有源区域与虚拟POLY线路延伸并重叠。有源区域和虚拟POLY线之间的重叠有助于减少有源区域边缘处的边缘缺陷。

15. 发明授权

US08601411B2 Pre-colored methodology of multiple patterning 有权
公开(公告)号：US08601411B2
公开(公告)日：2013-12-03
申请号：US13586177
申请日：2012-08-15
申请人： Yen-Huei Chen , Wei Min Chan , Hung-Jen Liao , Jonathan Tsung-Yung Chang
发明人： Yen-Huei Chen , Wei Min Chan , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5068 , G06F2217/12
摘要： Some embodiments relate to a method for pre-coloring data within an integrated chip layout to avoid overlay errors that result from mask misalignment during multiple patterning lithography. The method may be performed by generating a graphical IC layout file containing an integrated chip layout having a plurality of IC shapes. The IC shapes within the graphical IC layout file are assigned a color during decomposition. The IC shapes are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. During mask building data associated with IC shapes that have been pre-colored is automatically sent to a same mask, regardless of the colors that are assigned to the shapes. Therefore, the pre-colored shapes are not assigned to a masked based upon a decomposition, but rather based upon the pre-coloring. By assigning IC shapes to a same mask through pre-coloring, overlay errors can be reduced.

16. 发明申请

US20130263065A1 PRE-COLORED METHODOLOGY OF MULTIPLE PATTERNING 有权
标题翻译：多彩图案的预色彩方法
公开(公告)号：US20130263065A1
公开(公告)日：2013-10-03
申请号：US13586177
申请日：2012-08-15
申请人： Yen-Huei Chen , Wei Min Chan , Hung-Jen Liao , Jonathan Tsung-Yung Chang
发明人： Yen-Huei Chen , Wei Min Chan , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5068 , G06F2217/12
摘要： Some embodiments relate to a method for pre-coloring data within an integrated chip layout to avoid overlay errors that result from mask misalignment during multiple patterning lithography. The method may be performed by generating a graphical IC layout file containing an integrated chip layout having a plurality of IC shapes. The IC shapes within the graphical IC layout file are assigned a color during decomposition. The IC shapes are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. During mask building data associated with IC shapes that have been pre-colored is automatically sent to a same mask, regardless of the colors that are assigned to the shapes. Therefore, the pre-colored shapes are not assigned to a masked based upon a decomposition, but rather based upon the pre-coloring. By assigning IC shapes to a same mask through pre-coloring, overlay errors can be reduced.
摘要翻译：一些实施例涉及用于在集成芯片布局内预先着色数据的方法，以避免在多次图案化光刻期间由掩模未对准而产生的重叠误差。该方法可以通过生成包含具有多个IC形状的集成芯片布局的图形IC布局文件来执行。图形IC布局文件中的IC形状在分解过程中会分配一种颜色。 IC形状进一步预先着色，以故意将预色数据分配给相同的掩码。在掩模建立过程中，与预先着色的IC形状相关联的数据将自动发送到相同的掩码，而不管分配给形状的颜色如何。因此，预先着色的形状不是基于分解而分配给掩蔽的，而是基于预着色。通过预先着色将IC形状分配给相同的掩模，可以减少重叠错误。

17. 发明申请

US20120327730A1 SRAM Differential Voltage Sensing Apparatus 有权
标题翻译： SRAM差压检测装置
公开(公告)号：US20120327730A1
公开(公告)日：2012-12-27
申请号：US13169511
申请日：2011-06-27
申请人： Yen-Huei Chen , Kun-hsi Li , Shao-Yu Chou , Hung-Jen Liao , Wei Min Chan
发明人： Yen-Huei Chen , Kun-hsi Li , Shao-Yu Chou , Hung-Jen Liao , Wei Min Chan
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C7/12 , G11C7/062 , G11C11/419
摘要： An SRAM differential voltage sensing apparatus is coupled to a memory circuit. The memory circuit comprises a memory bank, a plurality of bit lines, a plurality of data lines coupled to the plurality of bit lines via a plurality of transmission gates and a sense amplifier. When the sense amplifier operates in a characterization mode, the transmission gates and pre-charge circuits are turned off. The differential voltage sensing apparatus applies a characterization signal to the sense amplifier and obtains the parameters of the memory circuit through a trial and error process.
摘要翻译： SRAM差分电压感测装置耦合到存储器电路。存储器电路包括存储体，多个位线，经由多个传输门和读出放大器耦合到多个位线的多条数据线。当感测放大器在表征模式下工作时，传输门和预充电电路被关断。差分电压感测装置将表征信号应用于感测放大器，并通过试错过程获得存储器电路的参数。

18. 发明申请

US20090316498A1 CIRCUIT AND METHOD FOR VDD-TRACKING CVDD VOLTAGE SUPPLY 有权
标题翻译：用于VDD跟踪CVDD电压供应的电路和方法
公开(公告)号：US20090316498A1
公开(公告)日：2009-12-24
申请号：US12205243
申请日：2008-09-05
申请人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou
发明人： Yen-Huei Chen , Wei Min Chan , Shao-Yu Chou
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C11/413 , G11C5/147
摘要： Circuit and methods for providing the CVDD supply to the cells in an SRAM array while maintaining a desired VDD voltage. A circuit is described for tracking the VDD supply voltage and providing a CVDD supply for the SRAM cells that maintains an offset above VDD until a maximum voltage for the CVDD voltage is reached. The CVDD voltage supplies the word line drivers and the cells in an SRAM array, while the bit line precharge and the remaining circuitry is operated on the VDD supply. By maintaining a maximum offset between the voltage CVDD and the supply voltage VDD, the SRAM will have the required static noise margins for reliable operation, while a lowered VDD_min voltage may also be obtained. A method for supplying a CVDD voltage to an SRAM cell array is disclosed where the CVDD voltage tracks a VDD supply voltage plus a predetermined offset voltage.
摘要翻译：用于向SRAM阵列中的单元提供CVDD电源同时保持期望的VDD电压的电路和方法。描述了用于跟踪VDD电源电压并为SRAM单元提供CVDD电源的电路，其保持高于VDD的偏移，直到达到CVDD电压的最大电压。 CVDD电压为SRAM阵列中的字线驱动器和单元供电，而位线预充电和其余电路在VDD电源上工作。通过保持电压CVDD和电源电压VDD之间的最大偏移，SRAM将具有用于可靠运行的所需静态噪声容限，同时也可获得降低的VDD_min电压。公开了一种向SRAM单元阵列提供CVDD电压的方法，其中CVDD电压跟踪VDD电源电压加上预定的偏移电压。

19. 发明授权

US09235675B2 Multidimensional monte-carlo simulation for yield prediction 有权
标题翻译：用于产量预测的多维蒙特卡罗模拟
公开(公告)号：US09235675B2
公开(公告)日：2016-01-12
申请号：US13078330
申请日：2011-04-01
申请人： Wei Min Chan , Shao-Yu Chou
发明人： Wei Min Chan , Shao-Yu Chou
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/10
摘要： An embodiment includes a computer program product for providing a yield prediction. The computer program product has a non-transitory computer readable medium with a computer program embodied thereon. The computer program comprises computer program code for obtaining a representation of a circuit. The circuit comprises a common path and a critical path, and the critical path represents multiple parallel paths. The computer program further comprises computer program code for obtaining a first table representing the common path and a second table representing the multiple parallel paths and computer program code for performing a variable based simulation based on the representation of the circuit, the first table, and the second table. The computer program also comprises computer program code for determining a result indication of each of the multiple parallel paths based on the variable based simulation compared with a predetermined specification.
摘要翻译：实施例包括用于提供成品率预测的计算机程序产品。该计算机程序产品具有其上包含计算机程序的非暂时计算机可读介质。计算机程序包括用于获得电路的表示的计算机程序代码。电路包括公共路径和关键路径，关键路径表示多个并行路径。计算机程序还包括用于获得表示公共路径的第一表格的计算机程序代码和表示多个并行路径的第二表和用于基于电路，第一表和第二表的表示执行基于变量的模拟的计算机程序代码第二张桌子。计算机程序还包括用于基于与预定规范相比较的基于变量的模拟来确定多个并行路径中的每一个的结果指示的计算机程序代码。

20. 发明授权

US09389511B2 Methods of making patterned structures of materials, patterned structures of materials, and methods of using same 有权
标题翻译：制造材料的图案结构，材料的图案化结构及其使用方法的方法
公开(公告)号：US09389511B2
公开(公告)日：2016-07-12
申请号：US14005964
申请日：2012-03-19
申请人： Evan L. Schwartz , Wei Min Chan , Jin-Kyun Lee , Sandip Tiwari , Christopher K. Ober
发明人： Evan L. Schwartz , Wei Min Chan , Jin-Kyun Lee , Sandip Tiwari , Christopher K. Ober
IPC分类号： G03F7/26 , G03F7/16 , H01L21/027 , B81C1/00 , G03F7/038 , G03F7/00
CPC分类号： G03F7/16 , B81C1/00031 , B81C2201/0149 , G03F7/0002 , G03F7/038 , H01L21/027 , Y10T428/24851
摘要： A method for forming patterns of organic polymer materials. The method can be used to form a layer with two patterned organic polymer materials. The photoresist and solvents used in the photoresist deposition and removal steps do not substantially affect the organic polymer materials.
摘要翻译：一种形成有机聚合物材料图案的方法。该方法可用于形成具有两个图案化有机聚合物材料的层。在光致抗蚀剂沉积和去除步骤中使用的光致抗蚀剂和溶剂基本上不影响有机聚合物材料。

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