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11. 发明申请

US20100314685A1 CHARGING PROTECTION DEVICE 有权
标题翻译：充电保护装置
公开(公告)号：US20100314685A1
公开(公告)日：2010-12-16
申请号：US12483737
申请日：2009-06-12
申请人： Jingrong Zhou , David Wu , James F. Buller
发明人： Jingrong Zhou , David Wu , James F. Buller
IPC分类号： H01L27/06 , H01L21/77
CPC分类号： H01L27/0255 , H01L21/84 , H01L27/1203
摘要： Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.
摘要翻译：形成具有改进的电荷保护的浅沟槽隔离绝缘体上硅（SOI）器件。实施例包括作为充电保护装置的SOI膜二极管和P +衬底结。实施例还包括从SOI晶体管漏极，通过导电触点，金属线，第二导电触点，与晶体管隔离的SOI二极管，第三导电触点，第二导线和第四导电触点的导电路径到SOI衬底的体硅层中的P +掺杂的衬底接触。

12. 发明授权

US07761838B2 Method for fabricating a semiconductor device having an extended stress liner 有权
标题翻译：制造具有延伸应力衬垫的半导体器件的方法
公开(公告)号：US07761838B2
公开(公告)日：2010-07-20
申请号：US11861492
申请日：2007-09-26
申请人： Zhonghai Shi , Mark Michael , Donna Michael, legal representative , David Wu , James F. Buller , Jingrong Zhou , Akif Sultan
发明人： Zhonghai Shi , Mark Michael , David Wu , James F. Buller , Jingrong Zhou , Akif Sultan
IPC分类号： G06F17/50 , H01L21/8238
CPC分类号： H01L21/823807 , H01L29/78 , H01L29/7843
摘要： The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.
摘要翻译：本文所述的技术和技术涉及自动创建与半导体基晶体管器件一起使用的应力衬垫的光致抗蚀剂掩模。应力衬垫掩模是利用自动设计工具生成的，其利用与晶片上的特征，器件和结构对应的布局数据。产生的应力衬垫掩模（以及使用应力衬垫掩模制造的晶片）限定了延伸超出晶体管区域的边界并进入晶片的应力不敏感区域的应力衬垫覆盖区域。延伸的应力衬垫通过提供额外的压缩/拉伸应力来进一步提高相应晶体管的性能。

13. 发明授权

US07576357B1 System for characterization of low-k dielectric material damage 有权
标题翻译：低k电介质损伤表征系统
公开(公告)号：US07576357B1
公开(公告)日：2009-08-18
申请号：US11259572
申请日：2005-10-26
申请人： Jianhong Zhu , David Wu
发明人： Jianhong Zhu , David Wu
IPC分类号： H01L23/58
CPC分类号： H01L22/14 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A method of detecting damage to at least one dielectric layer in an IC die by determining a capacitance factor. The capacitance factor can be used to determine damage in a low-k dielectric material. A system for detecting damage can include a conductive line structure for measuring capacitance and software or a device for determining the capacitance to determine the damage.
摘要翻译：一种通过确定电容因子来检测IC芯片中的至少一个电介质层的损伤的方法。电容因数可用于确定低k电介质材料的损伤。用于检测损伤的系统可以包括用于测量电容和软件的导线结构或用于确定电容以确定损坏的装置。

14. 发明授权

US07670932B2 MOS structures with contact projections for lower contact resistance and methods for fabricating the same 有权
标题翻译：具有用于较低接触电阻的接触突起的MOS结构及其制造方法
公开(公告)号：US07670932B2
公开(公告)日：2010-03-02
申请号：US11762133
申请日：2007-06-13
申请人： Jianhong Zhu , Fred Hause , David Wu
发明人： Jianhong Zhu , Fred Hause , David Wu
IPC分类号： C12N15/75
CPC分类号： H01L21/28518 , H01L21/28247 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/7833
摘要： MOS structures with contact projections for lower contact resistance and methods for fabricating such MOS structures have been provided. In an embodiment, a method comprises providing a semiconductor substrate, fabricating a gate stack on the substrate, and forming a contact projection on the substrate. Ions of a conductivity-determining type are implanted within the substrate using the gate stack as an ion implantation mask to form impurity-doped regions within the substrate. A metal silicide layer is formed on the contact projection and a contact is formed to the metal silicide layer. The contact is in electrical communication with the impurity-doped regions via the contact projection.
摘要翻译：已经提供了具有用于较低接触电阻的接触突起的MOS结构以及用于制造这种MOS结构的方法。在一个实施例中，一种方法包括提供半导体衬底，在衬底上制造栅极堆叠，以及在衬底上形成接触突起。使用栅极堆叠作为离子注入掩模将电导率确定类型的离子注入到衬底内，以在衬底内形成杂质掺杂区域。在接触突起上形成金属硅化物层，并且与金属硅化物层形成接触。触点通过接触突起与杂质掺杂区电连通。

15. 发明授权

US07271047B1 Test structure and method for measuring the resistance of line-end vias 失效
标题翻译：用于测量线端通孔电阻的测试结构和方法
公开(公告)号：US07271047B1
公开(公告)日：2007-09-18
申请号：US11327641
申请日：2006-01-06
申请人： Jianhong Zhu , Mark Michael , David Wu
发明人： Jianhong Zhu , Mark Michael , David Wu
IPC分类号： H01L21/8238
CPC分类号： H01L22/34 , H01L22/14
摘要： A test structure and methods of using and making the same are provided. In one aspect, a test structure is provided that includes a first conductor that has a first end and a second conductor that has a second end positioned above the first end. A third conductor is positioned between the first end of the first conductor and the second end of the second conductor. A first electrode is coupled to the first conductor at a first distance from the third conductor and a second electrode coupled to the first conductor at a second distance from the third conductor. A third electrode is coupled to the second conductor at a third distance from the third conductor and a fourth electrode is coupled to the second conductor at a fourth distance from the third conductor. The first through fourth electrodes provide voltage sense taps and the first and second conductors provide current sense taps from which the resistance of the third conductor may be derived.
摘要翻译：提供了测试结构及其使用和制造方法。在一个方面，提供一种测试结构，其包括具有第一端和第二导体的第一导体，第二导体具有位于第一端上方的第二端。第三导体位于第一导体的第一端和第二导体的第二端之间。第一电极以距离第三导体第一距离的第一导体耦合到第一导体，第二电极以距离第三导体第二距离的方式耦合到第一导体。第三电极以距离第三导体第三距离的方式耦合到第二导体，并且第四电极在距离第三导体的第四距离处耦合到第二导体。第一至第四电极提供电压检测抽头，并且第一和第二导体提供电流检测抽头，从该第三导体提供第三导体的电阻。

16. 发明授权

US08003466B2 Method of forming multiple fins for a semiconductor device 有权
标题翻译：形成半导体器件的多个翅片的方法
公开(公告)号：US08003466B2
公开(公告)日：2011-08-23
申请号：US12099726
申请日：2008-04-08
申请人： Zhonghai Shi , David Wu , Jingrong Zhou , Ruigang Li
发明人： Zhonghai Shi , David Wu , Jingrong Zhou , Ruigang Li
IPC分类号： H01L21/336 , H01L21/00 , H01L21/84 , H01L21/338 , H01L21/8234 , H01L21/3205 , H01L21/4763 , H01L27/148 , H01L29/66 , H01L29/76 , H01L21/12 , H01L27/088
CPC分类号： H01L21/823437 , H01L21/823431 , H01L29/66795 , H01L29/6681 , H01L29/785
摘要： A fabrication process for a FinFET device is provided. The process begins by providing a semiconductor wafer having a layer of conductive material such as silicon. A whole-field arrangement of fins is then formed from the layer of conductive material. The whole-field arrangement of fins includes a plurality of conductive fins having a uniform pitch and a uniform fin thickness. Next, a cut mask is formed over the whole-field arrangement of fins. The cut mask selectively masks sections of the whole-field arrangement of fins with a layout that defines features for a plurality of FinFET devices. The cut mask is used to remove a portion of the whole-field arrangement of fins, the portion being unprotected by the cut mask. The resulting fin structures are used to complete the fabrication of the FinFET devices.
摘要翻译：提供了一种用于FinFET器件的制造工艺。该过程开始于提供具有诸如硅的导电材料层的半导体晶片。然后由导电材料层形成翅片的全场排列。翅片的全场布置包括具有均匀间距和均匀翅片厚度的多个导电翅片。接下来，在翅片的整个场布置上形成切割掩模。切割掩模选择性地屏蔽翅片的全场布置的部分，其布局限定了用于多个FinFET器件的特征。切割掩模用于去除翅片的全场排列的一部分，该部分未被切割掩模保护。所得到的翅片结构用于完成FinFET器件的制造。

17. 发明授权

US08329519B2 Methods for fabricating a semiconductor device having decreased contact resistance 有权
标题翻译：制造具有降低的接触电阻的半导体器件的方法
公开(公告)号：US08329519B2
公开(公告)日：2012-12-11
申请号：US13305449
申请日：2011-11-28
申请人： Zhonghai Shi , David Wu , Mark Michael , Donna Michael, legal representative
发明人： Zhonghai Shi , David Wu , Mark Michael
IPC分类号： H01L27/12
CPC分类号： H01L29/41733 , H01L21/28518 , H01L21/76897 , H01L23/485 , H01L27/1203 , H01L29/66772 , H01L29/78654 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.
摘要翻译：提供了具有改善的接触电阻的半导体器件和制造这种半导体器件的方法。这些半导体器件包括半导体器件结构和接触。在半导体器件结构的表面部分和侧壁部分处，触点电耦合到半导体器件结构。

18. 发明授权

US07704320B2 Colloidal crystallization via applied fields 有权
标题翻译：通过应用场的胶体结晶
公开(公告)号：US07704320B2
公开(公告)日：2010-04-27
申请号：US10838908
申请日：2004-05-03
申请人： David W. M. Marr , Tieying Gong , David Wu
发明人： David W. M. Marr , Tieying Gong , David Wu
IPC分类号： C30B30/04
CPC分类号： C30B7/00 , C30B29/54
摘要： The methods provided use external fields such as light and electricity as a means of directing the crystallization of concentrated colloidal systems. Not only can nucleation be directed, crystal melting can be carefully controlled and light-induced crystal diffraction used as a means of directing light propagation. A number of factors play a significant role on the crystallization rate and location, including the intensity of the light field, the magnitude of the electric field, the colloid concentration, the colloid size, and the colloid composition. In varying these parameters, kinetics in these processes are extremely fast when compared to traditional colloidal crystallization approaches.
摘要翻译：提供的方法使用诸如光和电的外部领域作为指导浓缩胶体体系的结晶的手段。成核不仅可以引导，晶体熔化也可以小心控制，光诱导的晶体衍射用作引导光传播的手段。许多因素对结晶速率和位置都起着重要的作用，包括光场强度，电场强度，胶体浓度，胶体尺寸和胶体组成。在改变这些参数时，与传统的胶体结晶方法相比，这些方法中的动力学非常快。

19. 发明申请

US20080165199A1 AUTOMATIC LOAD BALANCING OF A 3D GRAPHICS PIPELINE 有权
标题翻译： 3D图形管道的自动负载平衡
公开(公告)号：US20080165199A1
公开(公告)日：2008-07-10
申请号：US11621917
申请日：2007-01-10
申请人： Jian Wei , James M. Brown , David Wu
发明人： Jian Wei , James M. Brown , David Wu
IPC分类号： G06T1/20
CPC分类号： G06T15/005 , G06T1/20
摘要： A device has a processor for processing a vertex processing stage, a sub-screen dividing stage and a pixel rendering stage of a three-dimensional (3D) graphics pipeline. The processor includes processing threads which balance the work load of the 3D graphics pipeline by prioritizing processing for the pixel rendering stage over other stages. Each processing thread, operating in parallel and independently, checks a level of tasks in a Task list of sub-screen tasks. If the level is below a threshold value, empty or the sub-screen tasks are all locked, the processing thread loops to the vertex processing stage. Otherwise, the processing thread processes a sub-screen task during the pixel rendering stage.
摘要翻译：一种设备具有用于处理三维（3D）图形流水线的顶点处理阶段，子屏幕划分阶段和像素渲染阶段的处理器。该处理器包括处理线程，其平衡3D图形流水线的工作负载，通过对像素渲染阶段的处理优先于其他阶段。并行和独立运行的每个处理线程检查子屏幕任务的任务列表中的任务级别。如果该级别低于阈值，则清空或子屏幕任务都被锁定，则处理线程循环到顶点处理阶段。否则，处理线程在像素渲染阶段处理子屏幕任务。

20. 发明申请

US20070021217A1 AD decorative/ protecting structure for base of game machine 审中-公开
标题翻译： AD装饰/保护结构为游戏机的基地
公开(公告)号：US20070021217A1
公开(公告)日：2007-01-25
申请号：US11183795
申请日：2005-07-19
申请人： David Wu
发明人： David Wu
IPC分类号： A63F9/24
CPC分类号： G07F17/32 , G07F17/3216 , G07F17/3227
摘要： An advertising decorative and protecting structure for a base of a game machine, the structure has a base provided therein with a cash box, the base is provided on its top surface with members such as a display screen and a top light box as the components of the main body of the game machine; the base is provided beneath the top and on the rear of the front face thereof with a liftable transparent door plate; this liftable transparent door plate is assembled on the rear of it at least with an integrally formed illumination device, so that it can generate an illumination function by which light is penetrable to the outside during operating the game machine, and also can form a covering and protecting structure for the entire base. The structure can elevate the effect of decoration of the base of the game machine in order to attract consumers, and further to enhance the function of protection of the cash box.
摘要翻译：一种用于游戏机基座的广告装饰和保护结构，该结构在其中设置有一个现金箱，底座在其顶表面上设置有诸如显示屏和顶灯箱的部件作为游戏机的主体; 底座在其正面的顶部和后部设置有可升降的透明门板; 该可升降透明门板至少具有一体形成的照明装置，组装在其后部，从而能够在操作游戏机时产生光线可透过外部的照明功能，也可以形成遮盖物保护整个基地的结构。结构可以提升游戏机底座的装饰效果，吸引消费者，进一步提升保护箱的功能。

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