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11. 发明申请

US20070166859A1 Array substrate for liquid crystal display device and manufacturing method thereof 有权
标题翻译：液晶显示装置用阵列基板及其制造方法
公开(公告)号：US20070166859A1
公开(公告)日：2007-07-19
申请号：US11646550
申请日：2006-12-28
申请人： Hye Lee , Jae Oh
发明人： Hye Lee , Jae Oh
IPC分类号： H01L21/00
CPC分类号： H01L27/124 , G02F1/136213 , G02F1/1368 , H01L27/1214 , H01L27/1288 , H01L29/4908
摘要： An array substrate for an LCD device and a manufacturing method thereof. The array substrate includes: a gate line, a gate electrode, a gate pad, and a pixel electrode formed on the substrate; a gate insulation layer formed on the substrate to expose the gate line and the pixel electrode; a source electrode connected to a data line crossing the gate line, a drain electrode facing the source electrode with a channel interposed, a data pad formed at one end of the data line, and a capacitor electrode overlapping portions of the pixel electrode and the gate line; a semiconductor layer constituting the channel between the source electrode and the drain electrode; first, second, third, and fourth contact holes formed in the gate pad, the data pad, the capacitor electrode, and the drain electrode, respectively; and first through fourth contact electrodes formed in the first through fourth contact holes, respectively.
摘要翻译：一种LCD装置用阵列基板及其制造方法。阵列基板包括：栅极线，栅电极，栅极焊盘和形成在基板上的像素电极; 栅极绝缘层，形成在所述衬底上以暴露所述栅极线和所述像素电极; 连接到与栅极线交叉的数据线的源极电极，与源极电极相对的沟道插入的漏电极，形成在数据线的一端的数据焊盘和电容器电极，重叠部分的像素电极和栅极线; 构成源电极和漏电极之间的沟道的半导体层; 分别形成在栅极焊盘，数据焊盘，电容器电极和漏极电极中的第一，第二，第三和第四接触孔; 以及形成在第一至第四接触孔中的第一至第四接触电极。

12. 发明申请

US20070117238A1 Liquid crystal display device and method for fabricating the same 有权
标题翻译：液晶显示装置及其制造方法
公开(公告)号：US20070117238A1
公开(公告)日：2007-05-24
申请号：US11473141
申请日：2006-06-23
申请人： Jae Oh , Soopool Kim
发明人： Jae Oh , Soopool Kim
IPC分类号： H01L21/00 , H01L31/00
CPC分类号： G02F1/1368 , G02F2001/136231 , G02F2001/136295
摘要： A method for fabricating a liquid crystal display (LCD) device includes: forming a gate line, a gate electrode, and a gate pad electrode on a substrate; sequentially forming a gate insulating layer, a semiconductor layer and a metal layer on an entire surface of the substrate including the gate electrode; forming a first photoresist on the metal layer; patterning the semiconductor layer, a data line, source and drain electrodes, and a data pad electrode by selectively etching the gate insulating layer, the semiconductor layer, and the metal layer using the first photoresist as a mask; forming a second photoresist to cover the gate pad electrode; forming a passivation layer on an entire surface of the substrate including the first and second photoresists; removing the passivation layer on the first and second photoresists by lift-stripping the first and second photoresists; and forming a pixel electrode electrically connected to the drain electrode.
摘要翻译：一种制造液晶显示器（LCD）器件的方法，包括：在衬底上形成栅极线，栅极电极和栅极焊盘电极; 在包括栅电极的基板的整个表面上依次形成栅极绝缘层，半导体层和金属层; 在所述金属层上形成第一光致抗蚀剂; 通过使用第一光致抗蚀剂作为掩模选择性地蚀刻栅极绝缘层，半导体层和金属层来图案化半导体层，数据线，源极和漏极以及数据焊盘电极; 形成第二光致抗蚀剂以覆盖所述栅极焊盘电极; 在包括第一和第二光致抗蚀剂的基板的整个表面上形成钝化层; 通过剥离第一和第二光致抗蚀剂来去除第一和第二光致抗蚀剂上的钝化层; 以及形成与漏电极电连接的像素电极。

13. 发明申请

US20060211185A1 Method for manufacturing transistor in semiconductor device 失效
标题翻译：在半导体器件中制造晶体管的方法
公开(公告)号：US20060211185A1
公开(公告)日：2006-09-21
申请号：US11154458
申请日：2005-06-16
申请人： Yong Kim , Se Jang , Jae Oh
发明人： Yong Kim , Se Jang , Jae Oh
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L21/823437 , H01L21/823412 , H01L21/823425 , H01L29/66537 , H01L29/6659 , H01L29/66621 , H01L29/7834
摘要： Disclosed herein is a method for manufacturing a transistor in a semiconductor device, which can improve the refresh characteristics of the device. The method comprises the steps of: providing a silicon substrate having active and field regions defined thereon; performing a first channel ion implantation process into the silicon substrate; sequentially forming a hard mask film and a photoresist pattern exposing a gate formation region on the substrate into which the first channel ion implantation process has been performed; performing a second channel ion implantation process into the substrate at a higher concentration than that of the first ion implantation process using the photoresist pattern as an ion implantation mask, so as to form doped regions in the substrate at the gate formation region and both sides adjacent thereto; etching a hard mask film using the photoresist pattern as an etch barrier; removing the photoresist pattern; etching the substrate using a portion of the hard mask film remaining after the etching as an etch barrier, so as to form a groove; removing the hard mask film remaining after the etching; forming a gate in the groove of the substrate from which the hard mask film has been removed; and forming source and drain regions on the substrate at both sides of the gate.
摘要翻译：这里公开了一种用于制造半导体器件中的晶体管的方法，其可以提高器件的刷新特性。该方法包括以下步骤：提供其上限定有活性和场区的硅衬底; 对硅衬底进行第一沟道离子注入工艺; 顺序地形成硬掩模膜和曝光已经进行了第一沟道离子注入工艺的衬底上的栅极形成区的光致抗蚀剂图案; 以比使用光致抗蚀剂图案作为离子注入掩模的第一离子注入工艺更高的浓度进行衬底中的第二沟道离子注入工艺，以便在栅极形成区域和两侧相邻的衬底中形成掺杂区域到; 使用光致抗蚀剂图案蚀刻硬掩模膜作为蚀刻阻挡层; 去除光致抗蚀剂图案; 使用蚀刻后残留的硬掩模膜的一部分作为蚀刻阻挡层蚀刻基板，以形成凹槽; 去除蚀刻后残留的硬掩模膜; 在已经去除了硬掩模膜的基板的凹槽中形成栅极; 以及在栅极两侧的衬底上形成源区和漏区。

14. 发明申请

US20060149029A1 Diamine compound having dendron side chain and liquid crystal aligning agent using same 审中-公开
标题翻译：具有枝晶侧链的二胺化合物和使用其的液晶取向剂
公开(公告)号：US20060149029A1
公开(公告)日：2006-07-06
申请号：US11221156
申请日：2005-09-06
申请人： Jae Oh , Moo Lee , Bum Lee , O Kwon , Won Dong , Yusuke Tsuda
发明人： Jae Oh , Moo Lee , Bum Lee , O Kwon , Won Dong , Yusuke Tsuda
IPC分类号： C08G69/08
CPC分类号： C08G73/10
摘要： Disclosed herein is a novel functional diamine compound having a dendron structure, polyamic acid which is produced using functional diamine, aromatic cyclic diamine, aliphatic cyclic acid dianhydride, and aromatic cyclic acid dianhydride, polyimide which is produced by imidizing polyamic acid, and an LC alignment film produced using polyimide. Even if the diamine compound is used in a small amount, it is possible to realize a high pretilt angle, thus the pretilt angle is easily controlled. Therefore, it can be used to produce an LC alignment film using a twisted nematic (TN) mode, in which the pretilt angle of liquid crystal is low, and a vertically aligned (VA) mode, which requires a high pretilt angle of about 90°.
摘要翻译：本文公开了具有树突状结构的新型官能二胺化合物，使用官能二胺，芳族环二胺，脂族环酸二酐和芳族环酸二酐制备的聚酰胺酸，通过酰亚胺化聚酰胺酸制备的聚酰亚胺和LC对准使用聚酰亚胺生产的薄膜。即使少量使用二胺化合物，也可以实现高预倾角，因此容易控制预倾角。因此，可以使用液晶的预倾角为低的扭曲向列（TN）模式和垂直取向（VA）模式来制造LC取向膜，其需要大约90°的预倾角 °。

15. 发明申请

US20060043812A1 Permanent magnet assisted synRM and method for imposing magnetic force thereon 有权
标题翻译：永磁辅助synRM及其上施加磁力的方法
公开(公告)号：US20060043812A1
公开(公告)日：2006-03-02
申请号：US11028314
申请日：2005-01-04
申请人： Dal Cheong , Kyung Lee , Hyun Shin , June Won , Jae Oh , Gil Lee
发明人： Dal Cheong , Kyung Lee , Hyun Shin , June Won , Jae Oh , Gil Lee
IPC分类号： H02K21/12
CPC分类号： H01F13/003 , H02K1/246 , H02K1/2766 , H02K15/03
摘要： A PMA (Permanent Magnet Assisted) synRM and a method for imposing a magnetic force thereon. Magnets are inserted into outer flux barriers of a plurality of flux barriers formed along the radius of a rotor, and bridges or slim portions are formed on inner flux barriers at positions corresponding to the positions of the magnets so that the magnetic force is imposed on the magnets through coils. Since the number of the flux barriers is sufficiently increased while the amount of the magnets consumed is decreased, the PMA synRM has increased efficiency and reduced production costs.
摘要翻译：一种PMA（永磁辅助）synRM及其上施加磁力的方法。将磁铁插入沿着转子半径形成的多个通量屏障的外部通量屏障中，并且在对应于磁体位置的位置处，在内部磁通屏障上形成桥梁或细长部分，使得磁力施加在磁铁通过线圈。由于磁通屏障的数量充分增加，而消耗的磁体的量减少，因此PMA synRM提高了效率并降低了生产成本。

16. 发明申请

US20050055419A1 Method and apparatus for platform independent network virtual memory (PINVM) hierarchy 审中-公开
标题翻译：用于平台独立网络虚拟内存（PINVM）层次结构的方法和装置
公开(公告)号：US20050055419A1
公开(公告)日：2005-03-10
申请号：US10848808
申请日：2004-05-19
申请人： Jae Oh
发明人： Jae Oh
IPC分类号： H04L29/06 , H04L29/08 , G06F15/167
CPC分类号： H04L67/16 , H04L29/06 , H04L67/14 , H04L69/10 , H04L69/329
摘要： A thin-client/server session is established using platform independent network virtual memory (PINVM). The server contains a collection of programs that are compiled for the client architecture. The client finds a server for PINVM. The server provides the client with the list of programs as well as the size of virtual memory space that will be allowed for the client to use. The client-side daemon process adjusts the available memory size so that the client OS thinks the memory size available is as large as the virtual memory size provided by the server during the session. The network virtual memory hierarchy is established, with the server's memory and hard disk attached to the client's physical memory hierarchy. After the client selects a program to launch, the server creates a virtual address space for the client program using the network memory hierarchy established. The program can now run on the client.
摘要翻译：使用独立于平台的网络虚拟内存（PINVM）建立瘦客户端/服务器会话。服务器包含为客户端架构编译的程序集合。客户端找到一个用于PINVM的服务器。服务器为客户端提供程序列表以及允许客户端使用的虚拟内存空间的大小。客户端守护进程调整可用的内存大小，以便客户端操作系统认为可用的内存大小与会话期间由服务器提供的虚拟内存大小一样大。建立网络虚拟内存层次结构，服务器的内存和硬盘连接到客户端的物理内存层次结构。客户端选择程序启动后，服务器将使用建立的网络内存层次结构为客户端程序创建一个虚拟地址空间。该程序现在可以在客户端上运行。

17. 发明申请

US20080005763A1 Broadcast receiver and method for performing closed caption 审中-公开
标题翻译：广播接收机和执行闭路字幕的方法
公开(公告)号：US20080005763A1
公开(公告)日：2008-01-03
申请号：US11819466
申请日：2007-06-27
申请人： Jae Oh
发明人： Jae Oh
IPC分类号： H04N7/10
CPC分类号： H04N7/0882
摘要： A host comprises a host controller configured to receive a first call for a specified attribute for closed caption from an application program; and the host controller further configured to return a predefined value to the application program or to perform exception handling in response to the first call when the specified attribute for closed caption is not supported by the host. And, the host controller is further configured to receive a second call requesting an array of available attributes for closed caption from the application program and to return the array of available attributes to the application program in response to the second call. Also, the host controller is further configured to return an array of available attributes for closed caption to the application program in response to the first call when the specified attribute for closed caption is not supported by the host.
摘要翻译：主机包括：主机控制器，被配置为从应用程序接收用于闭路字幕的指定属性的第一呼叫; 并且所述主机控制器还被配置为当所述主机不支持所述用于隐藏字幕的所述指定属性时，响应于所述第一呼叫，将预定义值返回给所述应用程序或执行异常处理。而且，所述主机控制器进一步被配置为从所述应用程序接收请求用于隐藏字幕的可用属性数组的第二呼叫，并响应于所述第二呼叫将所述可用属性阵列返回到所述应用程序。此外，主机控制器还被配置为当主机不支持用于隐藏字幕的指定属性时，响应于第一次呼叫，将用于隐藏字幕的可用属性的数组返回给应用程序。

18. 发明申请

US20070218577A1 Liquid crystal display panel and fabricating method thereof 有权
公开(公告)号：US20070218577A1
公开(公告)日：2007-09-20
申请号：US11643653
申请日：2006-12-22
申请人： Byung Ahn , Soon Yoo , Oh Kwon , Youn Chang , Heung Cho , Seung Nam , Jae Oh
发明人： Byung Ahn , Soon Yoo , Oh Kwon , Youn Chang , Heung Cho , Seung Nam , Jae Oh
IPC分类号： H01L21/00
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136236 , H01L27/124 , H01L27/1288 , H01L29/66742
摘要： A liquid crystal display (LCD) panel is fabricated with a reduced number of mask processes and includes a thin film transistor (TFT) array substrate and a color filter array substrate. The TFT array substrate includes gate and data lines insulatively crossing each other to define a pixel area, a TFT provided at the crossing of the gate and data lines, a passivation film protecting the TFT, a pixel electrode partially overlapped by the TFT, a gate pad connected to the gate line, and a data pad connected to the data line. The gate line, the gate and data pads, and the pixel electrode include a transparent conductive material. A gate metal material is on the transparent conductive material where the TFT partially overlaps the pixel electrode. The passivation film over the gate and data pads is removed to expose the transparent conductive material included within the gate and data pads.

19. 发明申请

US20060246671A1 Method of fabricating a transistor having a triple channel in a memory device 有权
标题翻译：在存储器件中制造具有三通道的晶体管的方法
公开(公告)号：US20060246671A1
公开(公告)日：2006-11-02
申请号：US11155833
申请日：2005-06-17
申请人： Se Jang , Yong Kim , Jae Oh
发明人： Se Jang , Yong Kim , Jae Oh
IPC分类号： H01L21/336 , H01L21/76
CPC分类号： H01L29/7851 , H01L27/105 , H01L27/1052 , H01L27/10876 , H01L27/10879 , H01L29/66621 , H01L29/66795
摘要： Disclosed is a method for fabricating a transistor of a memory device capable of preventing voids from being created when forming a low-resistant gate electrode. The method includes the steps of forming an active area by etching a semiconductor substrate, forming a field oxide layer in the semiconductor substrate and forming a recess by etching the field oxide layer. A gate insulation layer is formed along an upper surface of the active area and an exposed portion of the active area. A gate electrode is formed on the field oxide layer such that the gate electrode extends across an upper portion of the active area while being overlapped with a channel area and the recess. The first conductive layer to be patterned has the same thickness, so the low-resistant gate electrode is easily fabricated without forming the voids.
摘要翻译：公开了一种制造存储器件的晶体管的方法，该方法能够防止在形成低电阻栅电极时产生空隙。该方法包括以下步骤：通过蚀刻半导体衬底形成有源区，在半导体衬底中形成场氧化物层，并通过蚀刻场氧化物层形成凹陷。栅极绝缘层沿有源区的上表面和有源区的暴露部分形成。栅极电极形成在场氧化物层上，使得栅极电极延伸跨过有源区域的上部，同时与沟道区域和凹部重叠。待图案化的第一导电层具有相同的厚度，因此在不形成空隙的情况下容易地制造低电阻栅电极。

20. 发明申请

US20060244055A1 Transistor structure of memory device and method for fabricating the same 有权
公开(公告)号：US20060244055A1
公开(公告)日：2006-11-02
申请号：US11201951
申请日：2005-08-10
申请人： Se Jang , Yong Kim , Jae Oh , Jae Roh , Hyun Sohn
发明人： Se Jang , Yong Kim , Jae Oh , Jae Roh , Hyun Sohn
IPC分类号： H01L29/94
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10826 , H01L27/10873 , H01L27/10879 , H01L29/66621 , H01L29/66795 , H01L29/7851
摘要： A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed between the gate electrode and the active area. Source and drain areas are formed in the active area. The transistor structure above defines a recessed transistor structure if it is sectioned along a source-drain line and defines a Fin transistor structure if it is sectioned along a gate line. The transistor structure ensures sufficient data retention time and improves the current drivability while lowering the back bias dependency of a threshold voltage.

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