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11. 发明申请

US20050067644A1 Device and a method for forming a capacitor device 失效
标题翻译：装置及形成电容器装置的方法
公开(公告)号：US20050067644A1
公开(公告)日：2005-03-31
申请号：US10677099
申请日：2003-09-30
申请人： Haoren Zhuang , Nicolas Nagel , Jenny Lian , Rainer Bruchhaus
发明人： Haoren Zhuang , Nicolas Nagel , Jenny Lian , Rainer Bruchhaus
IPC分类号： H01L21/02 , H01L21/8246 , H01L27/115 , H01L29/76
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/92
摘要： A device and method for forming a capacitor device comprises forming a substrate, forming a first interlayer dielectric layer on the substrate and forming two or more contact plugs through the substrate. A conducting layer is formed on the first interlayer dielectric layer and an electrode is formed on alternate ones of the contact plugs by etching the conducting layer. The etched electrodes are then coated with a ferroelectric layer. The ferroelectric layer is etched from the surfaces separating the contact plugs and additional electrodes are created by filling the spaces between the electrodes on alternate ones of the contact plugs with a conductive material to establish electrical contact between the plugs and the electrodes.
摘要翻译：用于形成电容器器件的器件和方法包括形成衬底，在衬底上形成第一层间电介质层，并通过衬底形成两个或更多个接触插塞。在第一层间电介质层上形成导电层，通过蚀刻导电层，在交替的接触插塞上形成电极。然后用铁电层涂覆蚀刻的电极。从分离接触塞的表面蚀刻铁电层，并且通过用导电材料填充交替的接触插塞上的电极之间的空间来产生附加电极，以建立插塞和电极之间的电接触。

12. 发明授权

US07041551B2 Device and a method for forming a capacitor device 失效
标题翻译：装置及形成电容器装置的方法
公开(公告)号：US07041551B2
公开(公告)日：2006-05-09
申请号：US10677099
申请日：2003-09-30
申请人： Haoren Zhuang , Nicolas Nagel , Jenny Lian , Rainer Bruchhaus
发明人： Haoren Zhuang , Nicolas Nagel , Jenny Lian , Rainer Bruchhaus
IPC分类号： H01L21/8242
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/92
摘要： A device and method for forming a capacitor device comprises forming a substrate, forming a first interlayer dielectric layer on the substrate and forming two or more contact plugs through the substrate. A conducting layer is formed on the first interlayer dielectric layer and an electrode is formed on alternate ones of the contact plugs by etching the conducting layer. The etched electrodes are then coated with a ferroelectric layer. The ferroelectric layer is etched from the surfaces separating the contact plugs and additional electrodes are created by filling the spaces between the electrodes on alternate ones of the contact plugs with a conductive material to establish electrical contact between the plugs and the electrodes.
摘要翻译：用于形成电容器器件的器件和方法包括形成衬底，在衬底上形成第一层间电介质层，并通过衬底形成两个或更多个接触插塞。在第一层间电介质层上形成导电层，通过蚀刻导电层，在交替的接触插塞上形成电极。然后用铁电层涂覆蚀刻的电极。从分离接触塞的表面蚀刻铁电层，并且通过用导电材料填充交替的接触插塞上的电极之间的空间来产生附加电极，以建立插塞和电极之间的电接触。

13. 发明授权

US07045837B2 Hardmask with high selectivity for Ir barriers for ferroelectric capacitor manufacturing 失效
标题翻译：用于铁电电容器制造的Ir屏障的高选择性硬掩模
公开(公告)号：US07045837B2
公开(公告)日：2006-05-16
申请号：US10356314
申请日：2003-01-31
申请人： Ulrich Egger , Haoren Zhuang , Yoshinoru Kumura , Kazuhiro Tomioka , Hiroyuki Kanaya
发明人： Ulrich Egger , Haoren Zhuang , Yoshinoru Kumura , Kazuhiro Tomioka , Hiroyuki Kanaya
IPC分类号： H01L29/76
CPC分类号： H01L28/65 , H01L21/32136 , H01L21/32139 , H01L28/55
摘要： The present invention provides a ferroelectric device relatively free of fences by using a hardmask having high etching selectivity relative to an underlying barrier layer. The present invention also includes a method for suppressing the fences clinging to the sidewalls of ferroelectric devices. Additionally, the present invention provides a ferroelectric device having a hardmask relatively thin compared to an underlying barrier layer when compared to prior art devices.
摘要翻译：本发明通过使用相对于下层阻挡层具有高蚀刻选择性的硬掩模来提供相对不含栅栏的铁电体元件。本发明还包括一种用于抑制附着在铁电体器件的侧壁上的栅栏的方法。此外，与现有技术的装置相比，本发明提供一种具有与下层阻挡层相比较薄的硬掩模的铁电体装置。

14. 发明授权

US07042705B2 Sidewall structure and method of fabrication for reducing oxygen diffusion to contact plugs during CW hole reactive ion etch processing 失效
标题翻译：在CW孔反应离子蚀刻处理期间用于减少氧扩散到接触塞的侧壁结构和制造方法
公开(公告)号：US07042705B2
公开(公告)日：2006-05-09
申请号：US10356690
申请日：2003-01-30
申请人： Haoren Zhuang , Ulrich Egger , Kazuhiro Tomioka , Jingyu Lian , Nicolas Nagel , Andreas Hilliger , Gerhard Beitel
发明人： Haoren Zhuang , Ulrich Egger , Kazuhiro Tomioka , Jingyu Lian , Nicolas Nagel , Andreas Hilliger , Gerhard Beitel
IPC分类号： H01G4/10
CPC分类号： H01L28/55 , H01L21/31116 , H01L28/57
摘要： The present invention provides a sidewall oxygen diffusion barrier and a method for fabricating the sidewall oxygen diffusion barrier that reduces the diffusion of oxygen into contact plugs during a CW hole reactive ion etch of a ferroelectric capacitor of an FeRAM device. In one embodiment the sidewall barrier is formed from a substrate fence. In another embodiment, the sidewall barrier is formed by etching back an oxygen barrier.
摘要翻译：本发明提供一种侧壁氧扩散阻挡层和制造侧壁氧扩散阻挡层的方法，该方法在FeRAM器件的铁电电容器的CW孔反应离子蚀刻期间减少氧气扩散到接触塞中。在一个实施例中，侧壁屏障由衬底围栏形成。在另一个实施例中，通过蚀刻回氧屏障来形成侧壁屏障。

15. 发明授权

US07001780B2 Method of fabrication of an FeRAM capacitor and an FeRAM capacitor formed by the method 失效
标题翻译：通过该方法形成FeRAM电容器和FeRAM电容器的制造方法
公开(公告)号：US07001780B2
公开(公告)日：2006-02-21
申请号：US10635140
申请日：2003-08-06
申请人： Haoren Zhuang , Ulrich Egger , Jingyu Lian , Stefan Gernhardt , Hiroyuki Kanaya
发明人： Haoren Zhuang , Ulrich Egger , Jingyu Lian , Stefan Gernhardt , Hiroyuki Kanaya
IPC分类号： H01L21/00
CPC分类号： H01L28/86 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/90
摘要： A ferroelectric device includes a bottom electrode on which are formed ferrocapacitor elements and, over the ferroelectric elements, top electrodes. The bottom electrodes are connected to lower layers of the device via conductive plugs, and the plugs and bottom electrodes are spaced apart by barrier elements of Ir and/or IrO2. The barrier elements are narrower than the bottom electrode elements, and are formed by a separate etching process. This means that Ir fences are not formed during the etching of the bottom electrode. Also, little Ir and/or IrO2 diffuses through the bottom electrode to the ferroelectric elements, and therefore there is little risk of damage to the ferroelectric material.
摘要翻译：铁电体元件包括底电极，其上形成有铁电体元件，并且在铁电元件上形成顶电极。底部电极通过导电插头连接到器件的下层，并且插头和底部电极被Ir和/或IrO 2的阻挡元件隔开。阻挡元件比底部电极元件窄，并且通过单独的蚀刻工艺形成。这意味着在底电极的蚀刻期间不形成Ir栅栏。此外，很少的Ir和/或IrO 2 <2>通过底部电极扩散到铁电体元件，因此几乎不会损坏铁电体材料的风险。

16. 发明申请

US20050045937A1 FENCE-FREE ETCHING OF IRIDIUM BARRIER HAVING A STEEP TAPER ANGLE 失效
标题翻译：具有椎弓根角度的UM。。。。。。。。。。。。。。。。
公开(公告)号：US20050045937A1
公开(公告)日：2005-03-03
申请号：US10654376
申请日：2003-09-03
申请人： Ulrich Egger , Haoren Zhuang , George Stojakovic , Kazuhiro Tomioka
发明人： Ulrich Egger , Haoren Zhuang , George Stojakovic , Kazuhiro Tomioka
IPC分类号： H01L21/02 , H01L21/3213 , H01L21/8246 , H01L21/00 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L28/60 , H01L21/32136 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： An Iridium barrier layer is between a contact plug and a bottom electrode of a capacitor. Etching is performed to pattern the bottom electrode and barrier layer using a fluorine-based recipe resulting in the formation of a first fence clinging to the sidewalls. Next the remaining barrier layer is etched using a CO-based recipe. A second fence is formed clinging to and structurally supported by the first fence. At the same time, the CO-based recipe etches away a substantial portion of the first fence to remove the structural support provided to the second fence. The second fence is therefore lifted-off from the sidewalls leaving the sidewalls substantially free of clinging fences. The etched barrier layer has a sidewall transition. The sidewalls have a relatively low taper angle above the sidewall transition and a relatively steep taper angle below the sidewall transition.
摘要翻译：铱屏障层位于电容器的接触插塞和底部电极之间。进行蚀刻以使用氟基配方对底部电极和阻挡层进行图案化，从而形成紧贴在侧壁上的第一栅栏。接下来，使用基于CO的配方蚀刻剩余的阻挡层。第二个围栏是由第一个围栏固定在结构上。同时，基于CO的配方消除了第一篱笆的大部分，以移除提供给第二篱笆的结构支撑。因此，第二围栏从侧壁脱离，留下侧壁基本上没有附着的栅栏。蚀刻的阻挡层具有侧壁过渡。侧壁在侧壁过渡之上具有相对较低的锥角，并且在侧壁过渡之下具有相对较陡的锥角。

17. 发明授权

US07015049B2 Fence-free etching of iridium barrier having a steep taper angle 失效
标题翻译：无ence蚀刻具有陡峭锥角的铱屏障
公开(公告)号：US07015049B2
公开(公告)日：2006-03-21
申请号：US10654376
申请日：2003-09-03
申请人： Ulrich Egger , Haoren Zhuang , George Stojakovic , Kazuhiro Tomioka
发明人： Ulrich Egger , Haoren Zhuang , George Stojakovic , Kazuhiro Tomioka
IPC分类号： H01L21/00
CPC分类号： H01L28/60 , H01L21/32136 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： An Iridium barrier layer is between a contact plug and a bottom electrode of a capacitor. Etching is performed to pattern the bottom electrode and barrier layer using a fluorine-based recipe resulting in the formation of a first fence clinging to the sidewalls. Next the remaining barrier layer is etched using a CO-based recipe. A second fence is formed clinging to and structurally supported by the first fence. At the same time, the CO-based recipe etches away a substantial portion of the first fence to remove the structural support provided to the second fence. The second fence is therefore lifted-off from the sidewalls leaving the sidewalls substantially free of clinging fences. The etched barrier layer has a sidewall transition. The sidewalls have a relatively low taper angle above the sidewall transition and a relatively steep taper angle below the sidewall transition.
摘要翻译：铱屏障层位于电容器的接触插塞和底部电极之间。进行蚀刻以使用氟基配方对底部电极和阻挡层进行图案化，从而形成紧贴在侧壁上的第一栅栏。接下来，使用基于CO的配方蚀刻剩余的阻挡层。第二个围栏是由第一个围栏固定在结构上。同时，基于CO的配方消除了第一篱笆的大部分，以移除提供给第二篱笆的结构支撑。因此，第二围栏从侧壁脱离，留下侧壁基本上没有附着的栅栏。蚀刻的阻挡层具有侧壁过渡。侧壁在侧壁过渡之上具有相对较低的锥角，并且在侧壁过渡之下具有相对较陡的锥角。

18. 发明申请

US20050070030A1 Device and method for forming a contact to a top electrode in ferroelectric capacitor devices 审中-公开
标题翻译：在铁电电容器件中形成与顶部电极的接触的装置和方法
公开(公告)号：US20050070030A1
公开(公告)日：2005-03-31
申请号：US10672308
申请日：2003-09-26
申请人： Stefan Gernhardt , Haoren Zhuang , Ulrich Egger
发明人： Stefan Gernhardt , Haoren Zhuang , Ulrich Egger
IPC分类号： H01L21/02 , H01L21/00
CPC分类号： H01L28/60
摘要： A device and method for fabricating a device comprises forming a substrate and forming a contact plug through the substrate. A first electrode is formed on the substrate and a dielectric layer is formed on the first electrode. A second electrode is formed on the ferroelectric layer and an interlayer dielectric layer is applied to the second electrode and exposed surfaces of the first electrode and the ferroelectric layer. The interlayer dielectric layer is subjected to a chemical mechanical polishing process to expose a surface of the second electrode and a metal layer is deposited onto the polished interlayer dielectric layer and the exposed surface of the second electrode. The metal layer is then etched to provide an interconnection pattern to the second electrode.
摘要翻译：用于制造器件的器件和方法包括形成衬底并通过衬底形成接触插塞。在基板上形成第一电极，在第一电极上形成电介质层。在铁电体层上形成第二电极，在第二电极和第一电极和铁电层的露出面上施加层间电介质层。对层间介电层进行化学机械抛光工艺以暴露第二电极的表面，并且将金属层沉积到抛光的层间介电层和第二电极的暴露表面上。然后蚀刻金属层以提供到第二电极的互连图案。

19. 发明授权

US06867053B2 Fabrication of a FeRAM capacitor using a noble metal hardmask 失效
标题翻译：使用贵金属硬掩模制造FeRAM电容器
公开(公告)号：US06867053B2
公开(公告)日：2005-03-15
申请号：US10629326
申请日：2003-07-28
申请人： Ulrich Egger , Haoren Zhuang , Rainer Bruchhaus
发明人： Ulrich Egger , Haoren Zhuang , Rainer Bruchhaus
IPC分类号： H01L21/02 , H01L21/311 , H01L21/3213 , H01L21/00 , H01L21/8234
CPC分类号： H01L28/55 , H01L21/31122 , H01L21/31144 , H01L21/32136 , H01L21/32139 , H01L28/65
摘要： A ferroelectric capacitor is fabricated using a noble metal hardmask. A hardmask is deposited on a top electrode of a capacitor stack comprising a ferroelectric layer sandwiched between the top electrode and a bottom electrode. The top electrode is patterned according to the pattern of the hardmask by etching at a first temperature. The top electrode serves as the noble metal hardmask and the ferroelectric layer is patterned according to the pattern of the top electrode at a second temperature lower than the first temperature, resulting in the top electrode having sidewalls beveled relative to a top surface of the top electrode etching. The bottom electrode is etched at a third temperature to form the capacitor.
摘要翻译：使用贵金属硬掩模制造铁电电容器。硬掩模沉积在电容器堆叠的顶部电极上，该电容器堆叠包括夹在顶部电极和底部电极之间的铁电层。根据硬掩模的图案，通过在第一温度下蚀刻来对顶部电极进行图案化。顶部电极用作贵金属硬掩模，并且铁电层根据顶部电极的图案在低于第一温度的第二温度下被图案化，导致顶部电极具有相对于顶部电极的顶表面倾斜的侧壁蚀刻。在第三温度下蚀刻底部电极以形成电容器。

20. 发明授权

US06762064B1 Process for fabrication of a ferrocapacitor 失效
标题翻译：制造铁电体的方法
公开(公告)号：US06762064B1
公开(公告)日：2004-07-13
申请号：US10417526
申请日：2003-04-17
申请人： Haoren Zhuang , Ulrich Egger , Kazuhiro Tomioka
发明人： Haoren Zhuang , Ulrich Egger , Kazuhiro Tomioka
IPC分类号： H01L2100
CPC分类号： H01L28/55 , H01L21/32139 , H01L27/11507 , H01L28/60
摘要： A process for the fabrication of a ferrocapacitor comprising depositing a first mask element 7 over a structure having a bottom electrode 1, a ferroelectric layer 3 and a top electrode 5. RIE etching is performed to remove portions of the top electrode 5 and the ferroelectric layer 3. Then a second hard mask element 9 is deposited over the first hardmask element. The second hard mask element is rounded by an etch back process, and its taper angle is controlled to be in the range 75-87°. A second RIE etching process is performed to remove portions of the bottom electrode 1. Due to the rounding of the second hard mask elements 9 low residues are formed on the sides of the etched bottom electrode 1.
摘要翻译：一种用于制造铁电体的方法，包括在具有底部电极1，铁电体层3和顶部电极5的结构上沉积第一掩模元件7.进行RIE蚀刻以去除顶部电极5和铁电层的部分然后，第二硬掩模元件9沉积在第一硬掩模元件上。第二个硬掩模元件通过回蚀工艺圆化，其锥角控制在75-87°的范围内。执行第二RIE蚀刻工艺以去除底部电极1的部分。由于第二硬掩模元件9的四舍五入，在蚀刻的底部电极1的侧面上形成低残留物。

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