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11. 发明授权

US5457405A Complementary logic recovered energy circuit 失效
标题翻译：互补逻辑恢复能量回路
公开(公告)号：US5457405A
公开(公告)日：1995-10-10
申请号：US364912
申请日：1994-12-27
申请人： William J. Ooms , Jerald A. Hallmark
发明人： William J. Ooms , Jerald A. Hallmark
IPC分类号： H03K19/00 , H03K19/096
CPC分类号： H03K19/0013 , H03K19/0019 , H03K19/0963
摘要： A circuit derives all power from a single clock input terminal and has no connections to separate power source or power sink terminals. The circuit configuration is applicable to many functions such as inverters, logic gates (NAND, NOR, etc.), and storage elements. When connected to form an inverter function, a current electrode of a first transistor is coupled to the clock input terminal and a control electrode is coupled to a signal input terminal while a second transistor has a current electrode coupled to the clock input terminal and a control electrode coupled the signal input terminal. Both transistors have a second current electrode coupled to an output of the inverter.
摘要翻译：电路从单个时钟输入端子获得所有电源，并且没有连接到单独的电源或电源端子。该电路配置适用于逆变器，逻辑门（NAND，NOR等）和存储元件等许多功能。当连接以形成反相器功能时，第一晶体管的电流电极耦合到时钟输入端子，并且控制电极耦合到信号输入端子，而第二晶体管具有耦合到时钟输入端子的电流电极和控制电极电极耦合信号输入端。两个晶体管都具有耦合到反相器的输出的第二电流电极。

12. 发明授权

US4125855A Integrated semiconductor crosspoint arrangement 失效
标题翻译：集成半导体交叉点布置
公开(公告)号：US4125855A
公开(公告)日：1978-11-14
申请号：US781790
申请日：1977-03-28
申请人： James A. Davis , William J. Ooms
发明人： James A. Davis , William J. Ooms
IPC分类号： H03K17/00 , H01L21/331 , H01L21/74 , H01L21/762 , H01L21/8224 , H01L23/535 , H01L27/082 , H01L27/102 , H01L29/08 , H01L29/73 , H03K17/62 , H03K17/66 , H03K17/68 , H04Q3/52 , H01L27/04
CPC分类号： H03K17/6221 , H01L21/743 , H01L21/762 , H01L23/535 , H01L27/0821 , H01L27/1022 , H03K17/668 , H03K17/68 , H04Q3/521 , H01L2924/0002 , H01L2924/3011
摘要： Symmetrical integrated transistors and drive circuitry provide low loss bilateral analog crosspoints for a switching matrix. Each crosspoint comprises a high performance PNP lateral transmission switching transistor and an associated NPN vertical drive transistor formed over a common n-type buried tub in a p-type substrate. Individual crosspoints, including the transmission transistor and the drive circuitry, are isolated by means of frame shaped p-type isolation regions lying outside the buried tub. The collector of the NPN drive transistor and the base of the PNP transmission transistor are ohmically connected by means of the buried tub. Accordingly, although the transmission transistor and the drive transistor are merged in a single isolation region, current drive to the PNP transistor is by means of the NPN transistor as a functionally independent device. The lateral PNP transistor comprises stripe shaped emitter and collector electrodes which are formed in a single step with the isolation region and the electrodes are of equal doping, size, and shape. Pluralities of such emitters and collectors which are respectively interconnected by surface metallizations may be utilized to increase the efficiency and the current carrying capacity of the transmission transistor.
摘要翻译：对称集成晶体管和驱动电路为开关矩阵提供低损耗的双向模拟交叉点。每个交叉点包括高性能PNP横向传输切换晶体管和形成在p型衬底中的公共n型埋置式桶上的相关联的NPN垂直驱动晶体管。包括传输晶体管和驱动电路在内的各个交叉点通过位于掩埋槽外部的框形的p型隔离区隔离开。 NPN驱动晶体管的集电极和PNP传输晶体管的基极通过埋地槽欧姆连接。因此，虽然传输晶体管和驱动晶体管合并在单个隔离区域中，但是通过作为功能无关的器件的NPN晶体管对PNP晶体管的电流驱动。横向PNP晶体管包括条形发射极和集电极，它们以隔离区形成一个单一步骤，并且电极具有相等的掺杂，尺寸和形状。分别通过表面金属化互连的这种发射器和集电器的多个可以用于提高传输晶体管的效率和载流能力。

13. 发明授权

US07342276B2 Method and apparatus utilizing monocrystalline insulator 有权
标题翻译：使用单晶绝缘子的方法和装置
公开(公告)号：US07342276B2
公开(公告)日：2008-03-11
申请号：US10861467
申请日：2004-06-07
申请人： William J. Ooms , Jerald A. Hallmark
发明人： William J. Ooms , Jerald A. Hallmark
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/19 , H01L31/113
CPC分类号： H01L28/55 , H01L21/28194 , H01L21/28202 , H01L21/31691 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/94
摘要： A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive element and substantially lattice matched to the semiconductor material.
摘要翻译：一种半导体器件，包括：半导体材料; 导电元件; 以及设置在半导体材料和导电元件之间并基本上与半导体材料晶格匹配的基本单晶绝缘体。

14. 发明授权

US06559471B2 Quantum well infrared photodetector and method for fabricating same 失效
标题翻译：量子阱红外光电探测器及其制造方法
公开(公告)号：US06559471B2
公开(公告)日：2003-05-06
申请号：US09733688
申请日：2000-12-08
申请人： Jeffrey M. Finder , William J. Ooms
发明人： Jeffrey M. Finder , William J. Ooms
IPC分类号： H01L2906
CPC分类号： H01L31/035245 , B82Y20/00 , H01L21/02381 , H01L21/02488 , H01L21/02505 , H01L21/02521 , H01L21/31691 , H01L31/0368 , H01L31/101 , Y02E10/50
摘要： High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer (204) on a silicon wafer (202). The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (206) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. Quantum well infrared photodetectors (200) can be grown on the high quality epitaxial monocrystalline material formed on such compliant substrates to create highly reliable devices having reduced costs.
摘要翻译：通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。实现顺应性衬底的形成的一种方法包括首先在硅晶片（202）上生长容纳缓冲层（204）。容纳缓冲层是通过氧化硅的非晶界面层（206）与硅晶片间隔开的单晶氧化物层。非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。容纳缓冲层与下面的硅晶片和上覆单晶层两者晶格匹配。通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。量子阱红外光电探测器（200）可以在形成于这种柔性衬底上的高质量外延单晶材料上生长，从而产生具有降低成本的高度可靠的器件。

15. 发明授权

US06367261B1 Thermoelectric power generator and method of generating thermoelectric power in a steam power cycle utilizing latent steam heat 失效
标题翻译：热电发电机及利用潜热蒸汽在蒸汽动力循环中产生热电功率的方法
公开(公告)号：US06367261B1
公开(公告)日：2002-04-09
申请号：US09703072
申请日：2000-10-30
申请人： Daniel S. Marshall , Jerald A. Hallmark , William J. Ooms
发明人： Daniel S. Marshall , Jerald A. Hallmark , William J. Ooms
IPC分类号： F01K1700
CPC分类号： H01L35/00 , F01K9/00
摘要： A thermoelectric power generator and method of generating thermoelectric power in a steam power cycle utilizing latent steam heat including a condenser, a heat source, such as steam, and at least one thermoelectric module. The condenser includes a plurality of condenser tubes each having included therein a heat extractor. The heat source is in communication with the condenser and is characterized as providing thermal energy to the condenser. The at least one thermoelectric module, including a plurality of thermoelectric elements, is positioned in communication with at least one of the plurality of condenser tubes so that thermal energy flows through the thermoelectric elements thereby generating electrical power.
摘要翻译：一种热电发电机和利用包括冷凝器，热源（例如蒸汽）和至少一个热电模块的潜热蒸汽热在蒸汽动力循环中产生热电功率的方法。冷凝器包括多个冷凝管，每个冷凝管每个都包括一个散热器。热源与冷凝器连通，其特征在于向冷凝器提供热能。包括多个热电元件的至少一个热电模块被定位成与多个冷凝器管中的至少一个连通，使得热能流过热电元件从而产生电力。

16. 发明授权

US06224669B1 Method for fabricating a semiconductor structure having a crystalline alkaline earth metal oxide interface with silicon 有权
标题翻译：制造具有与硅结晶的碱土金属氧化物界面的半导体结构的方法
公开(公告)号：US06224669B1
公开(公告)日：2001-05-01
申请号：US09662390
申请日：2000-09-14
申请人： Zhiyi Yi , Ravindranath Droopad , Corey Daniel Overgaard , Jamal Ramdani , Jay A. Curless , Jerald A. Hallmark , William J. Ooms , Jun Wang
发明人： Zhiyi Yi , Ravindranath Droopad , Corey Daniel Overgaard , Jamal Ramdani , Jay A. Curless , Jerald A. Hallmark , William J. Ooms , Jun Wang
IPC分类号： C03B2514
CPC分类号： H01L21/31691 , C30B23/02 , C30B25/02 , C30B29/16 , H01L21/31604 , H01L28/56
摘要： A method for fabricating a semiconductor structure comprises the steps of providing a silicon substrate (10) having a surface (12); forming on the surface of the silicon substrate an interface (14) comprising a single atomic layer of silicon, oxygen, and a metal; and forming one or more layers of a single crystal oxide (26) on the interface. The interface comprises an atomic layer of silicon, oxygen, and a metal in the form XSiO2, where X is a metal.
摘要翻译：一种制造半导体结构的方法包括以下步骤：提供具有表面（12）的硅衬底（10）; 在所述硅衬底的表面上形成包含硅，氧和金属的单原子层的界面（14）; 以及在界面上形成一层或多层单晶氧化物（26）。该界面包括硅，氧和XSiO 2形式的金属的原子层，其中X是金属。

17. 发明授权

US6097047A Ferroelectric semiconductor device, and ferroelectric semiconductor substrate 失效
标题翻译：铁电半导体器件和铁电半导体衬底
公开(公告)号：US6097047A
公开(公告)日：2000-08-01
申请号：US70063
申请日：1998-04-30
申请人： William J. Ooms , Jerald A. Hallmark , Daniel S. Marshall
发明人： William J. Ooms , Jerald A. Hallmark , Daniel S. Marshall
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/10 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66772 , H01L21/8234 , H01L29/1079 , H01L29/78391 , H01L29/78603 , H01L29/78645
摘要： A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) is manufactured from a substrate (11) that has a layer (14) of ferroelectric material sandwiched between a substrate (13) and a layer (16) of silicon. A gate structure (24) is formed on the layer (16) of silicon. A source region is formed in a portion of the layer (16) of silicon adjacent one side of the gate structure (24) and a drain region is formed in a portion of the layer (16) of silicon adjacent an opposing side of the gate structure (24).
摘要翻译：铁电半导体器件（10）和制造铁电半导体器件（10）的方法。铁电半导体装置（10）由具有夹在基板（13）和硅层（16）之间的铁电材料层（14）的基板（11）制成。在硅的层（16）上形成栅极结构（24）。源极区域形成在与栅极结构（24）的一侧相邻的硅的层（16）的一部分中，并且漏极区域形成在邻近栅极的相对侧的硅层（16）的一部分中结构（24）。

18. 发明授权

US5243206A Logic circuit using vertically stacked heterojunction field effect transistors 失效
标题翻译：使用垂直堆叠异步场效应晶体管的逻辑电路
公开(公告)号：US5243206A
公开(公告)日：1993-09-07
申请号：US724636
申请日：1991-07-02
申请人： X. Theodore Zhu , Jonathan K. Abrokwah , Herbert Goronkin , William J. Ooms , Carl L. Shurboff
发明人： X. Theodore Zhu , Jonathan K. Abrokwah , Herbert Goronkin , William J. Ooms , Carl L. Shurboff
IPC分类号： H01L21/8232 , H01L27/06 , H01L27/11 , H03K19/08
CPC分类号： H01L27/11 , H01L27/0605 , Y10S257/903
摘要： Logic circuits using a heterojunction field effect transistor structure having vertically stacked complementary devices is provided. A P-channel quantum well and an N-channel quantum well are formed near each other under a single gate electrode and separated from each other by a thin layer of barrier material. P-source and P-drain regions couple to the P-channel. N-source and N-drain regions couple to the N-channel. The P-source/drain regions are electrically isolated from the N-source/drain regions so the P-channel and N-channel devices may be interconnected to provide many logic functions.

19. 发明授权

US5049760A High speed complementary flipflop 失效
标题翻译：高速互补触发器
公开(公告)号：US5049760A
公开(公告)日：1991-09-17
申请号：US609538
申请日：1990-11-06
申请人： William J. Ooms
发明人： William J. Ooms
IPC分类号： H03K3/3562
CPC分类号： H03K3/35625
摘要： A complementary flipflop circuit is provided combining high speed with substantially zero DC current flow in standby mode between clock signal transitions. A differential input stage having n-channel transistors is gated by one phase of a clock signal for storing a complementary data input signal at the drains of p-channel load transistors which are cross-coupled to the first and second outputs of the differential input stage. The zero DC current flow is provided as the complementary configuration of the p-channel load transistors and the n-channel transistors of the differential input stage maintains isolation between the power supply conductors between transitions of the clock signal thereby reducing the average power consumption. The high operation bandwidth is achieved by using only a single p-channel transistor between the power supply conductors with gallium arsenide material.
摘要翻译：提供了一种互补的触发器电路，其在时钟信号转换之间在待机模式下组合高速和基本为零的直流电流。具有n沟道晶体管的差分输入级由一个时钟信号相位选通，用于在互相耦合到差分输入级的第一和第二输出的p沟道负载晶体管的漏极处存储互补数据输入信号。提供零直流电流作为p沟道负载晶体管的互补配置，并且差分输入级的n沟道晶体管在时钟信号的转变之间保持电源导体之间的隔离，从而降低平均功耗。通过在砷化镓材料的电源导体之间仅使用单个p沟道晶体管来实现高工作带宽。

20. 发明授权

US4316151A Phase locked loop frequency synthesizer using multiple dual modulus prescalers 失效
标题翻译：使用多个双模预分频器的锁相环频率合成器
公开(公告)号：US4316151A
公开(公告)日：1982-02-16
申请号：US121333
申请日：1980-02-13
申请人： William J. Ooms
发明人： William J. Ooms
IPC分类号： H03L7/18 , H03K23/66 , H03L7/193 , H03L7/197 , H03K21/36
CPC分类号： H03L7/193 , H03K23/667
摘要： An improved frequency synthesizer suitable for use in mobile and portable radio applications using multiple dual modulus prescalers to achieve high frequency operation and low current drain. A first high speed prescaler of limited size is used in conjunction with a second prescaler to avoid the use of one large high speed prescaler to attain high frequency operation. Consequently, the frequency synthesizer can be constructed using only a minimum amount of high speed, high current drain logic thereby reducing costs and power consumption.
摘要翻译：一种改进的频率合成器，适用于使用多个双模预分频器实现高频操作和低电流消耗的移动和便携式无线电应用。与第二个预分频器一起使用有限尺寸的第一个高速预分频器，以避免使用一个大型高速预分频器来实现高频操作。因此，频率合成器可以仅使用最小量的高速，高电流消耗逻辑来构造，从而降低成本和功耗。

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