会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 12. 发明申请
    • Write circuit of double data rate synchronous DRAM
    • 双数据速率同步DRAM的写电路
    • US20050141331A1
    • 2005-06-30
    • US10880381
    • 2004-06-29
    • Yong Cho
    • Yong Cho
    • G11C11/40G11C7/10G11C8/00
    • G11C7/1093G11C7/1072G11C7/1078G11C7/1096
    • Provided is a write circuit of a DDR SDRAM, in which a clock domain crossing is generated from a writing driver during a data write operation and a proper data is always transferred to a gio bus line by using the delay of an internal data strobe signal's falling for a certain amount of time as an input data strobe bar signal. Moreover, by using a skew detection circuit, it is possible to detect a skew tDQSS between a clock and a data strobe, and the skew tDQSS is automatically compensated by the skew compensation circuit. From the perspective of a timing error between the clock and the data strobe, therefore, the write operation of the DDR SDRAM has twice the timing margin (0.5tCK) compared to that of the related art. This means that a stable, high-speed write operation of the DDR SDRAM can be made possible.
    • 提供了DDR SDRAM的写入电路,其中在数据写入操作期间从写入驱动器产生时钟域交叉,并且通过使用内部数据选通信号的下降的延迟将适当的数据总是传送到gio总线 作为输入数据选通信号的一定时间。 此外,通过使用偏斜检测电路,可以检测时钟和数据选通之间的偏斜tDQSS,并且由偏斜补偿电路自动补偿偏斜tDQSS。 因此,从时钟与数据选通之间的定时误差的观点出发,与现有技术相比,DDR SDRAM的写操作具有两倍的时间裕度(0.5tCK)。 这意味着可以使DDR SDRAM的稳定的高速写操作成为可能。
    • 14. 发明授权
    • System and method for estimating duplicate data
    • 用于估计重复数据的系统和方法
    • US08793226B1
    • 2014-07-29
    • US11846033
    • 2007-08-28
    • Sandeep YadavDon TrimmerYong Cho
    • Sandeep YadavDon TrimmerYong Cho
    • G06F17/30
    • G06F17/30156
    • The present invention provides a system and method for estimating duplicate data in a storage system. A duplicate estimation application executes on a client of a storage system selects an element from an intended destination such as, e.g., a data store of the storage system. If the element is a file (or other data container), the application reads data from the file and computes a fingerprint of the read data. The computed fingerprint is then logged in a fingerprint database, which is illustratively stored on a storage device connected to the client executing the application. This process repeats until the entire file (or other data container) has been read and fingerprinted. Once all elements have been scanned, fingerprinted and recorded, the application identifies any unique entries within the fingerprint database. Utilizing this information, the application computes an estimated space savings that may be realized by employing a data de-duplication technique.
    • 本发明提供一种用于估计存储系统中的重复数据的系统和方法。 在存储系统的客户端上执行的重复估计应用从预期目的地(例如,存储系统的数据存储)中选择一个元素。 如果元素是文件(或其他数据容器),则应用程序从文件读取数据并计算读取数据的指纹。 然后将计算出的指纹记录在指纹数据库中,该指纹数据库被示例性地存储在连接到执行应用程序的客户端的存储设备上。 该过程重复,直到整个文件(或其他数据容器)已被读取和指纹。 一旦所有元素被扫描,指纹和记录,应用程序将识别指纹数据库中的任何唯一条目。 利用该信息,应用程序计算可以通过采用重复数据删除技术来实现的估计空间节省。
    • 17. 发明申请
    • ALGORITHM FOR THE AUTOMATIC DETERMINATION OF OPTIMAL AV AND VV INTERVALS
    • 用于自动确定最佳AV和VV间隔的算法
    • US20070213778A1
    • 2007-09-13
    • US11751250
    • 2007-05-21
    • John BurnesYong ChoDavid IgelLuc MongeonJohn RueterHarry StoneJody Zilinski
    • John BurnesYong ChoDavid IgelLuc MongeonJohn RueterHarry StoneJody Zilinski
    • A61N1/05
    • A61N1/3627A61N1/36521A61N1/3682A61N1/3684
    • Methods and devices for determining optimal Atrial to Ventricular (AV) pacing intervals and Ventricular to Ventricular (VV) delay intervals in order to optimize cardiac output. Impedance, preferably sub-threshold impedance, is measured across the heart at selected cardiac cycle times as a measure of chamber expansion or contraction. One embodiment measures impedance over a long AV interval to obtain the minimum impedance, indicative of maximum ventricular expansion, in order to set the AV interval. Another embodiment measures impedance change over a cycle and varies the AV pace interval in a binary search to converge on the AV interval causing maximum impedance change indicative of maximum ventricular output. Another method varies the right ventricle to left ventricle (VV) interval to converge on an impedance maximum indicative of minimum cardiac volume at end systole. Another embodiment varies the VV interval to maximize impedance change.
    • 用于确定最佳心房与心室(AV)起搏间隔和心室间室(VV)延迟间隔的方法和装置,以优化心输出量。 在选择的心脏周期时间内,跨心脏测量阻抗,优选亚阈值阻抗,作为腔室扩张或收缩的量度。 为了设定AV间隔,一个实施例测量长AV间隔上的阻抗以获得指示最大心室扩张的最小阻抗。 另一个实施例测量一个周期的阻抗变化,并且改变二进制搜索中的AV步速间隔以收敛于AV间隔,从而引起指示最大心室输出的最大阻抗变化。 另一种方法将右心室改变为左心室(VV)间隔,以收敛于指示最终心脏收缩最小心脏容积的阻抗最大值。 另一实施例改变VV间隔以最大化阻抗变化。
    • 20. 发明申请
    • ADDRESS LATCH SIGNAL GENERATION CIRCUIT AND ADDRESS DECODING CIRCUIT
    • 地址锁存信号发生电路和地址解码电路
    • US20060227623A1
    • 2006-10-12
    • US11164723
    • 2005-12-02
    • Yong Cho
    • Yong Cho
    • G11C7/10
    • G11C11/4087G11C8/18G11C11/4082
    • An address latch signal generation circuit and an address decoding circuit may generate an address latch signal capable of latching pre-decoded internal address signals. The circuits may include a plurality of address transition detectors, each of the address transition detectors receiving a plurality of internal address signals pre-decoded by a pre-decoder, detecting level transition states of the internal address signals, and generating a control signal which has a predetermined enable period; a first logic unit for performing a logic operation on the control signals received from the plurality of address transition detectors, and generating the result signal; and a latch signal output unit for performing synchronization with a disable time point of the result signal from the first logic unit, thereby generating the address latch signal.
    • 地址锁存信号产生电路和地址解码电路可产生能够锁存预解码的内部地址信号的地址锁存信号。 电路可以包括多个地址转换检测器,每个地址转换检测器接收由预解码器预解码的多个内部地址信号,检测内部地址信号的电平转换状态,并产生一个控制信号,该控制信号具有 预定使能期间; 第一逻辑单元,用于对从多个地址转换检测器接收的控制信号执行逻辑运算,并产生结果信号; 以及锁存信号输出单元,用于与来自第一逻辑单元的结果信号的禁用时间点执行同步,从而产生地址锁存信号。