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11. 发明授权

US07779232B2 Method and apparatus for dynamically managing instruction buffer depths for non-predicted branches 失效
标题翻译：用于动态管理非预测分支的指令缓冲区深度的方法和装置
公开(公告)号：US07779232B2
公开(公告)日：2010-08-17
申请号：US11845838
申请日：2007-08-28
申请人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
发明人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
IPC分类号： G06F9/42 , G06F9/312
CPC分类号： G06F9/3804
摘要： A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.
摘要翻译：用于动态管理非预测分支的指令缓冲器深度的方法和装置减少与低置信度分支预测条件相关联的浪费的能量和资源。分配用于指令线程的指令缓冲器的一部分用于存储预测的分支指令流，并且在高预测置信度条件下可以为零大小的另一部分被分配给非预测分支指令流。缓冲区的大小根据正在进行的预测置信度动态调整，提供了分支预测机制对给定指令线程的工作原理的测量。替代指令提取地址表可以与主提取地址寄存器保持多路复用，用于对指令高速缓存进行寻址，使得当分支指令被解析为非预测路径时，可以将指令流快速移位到非预测路径。

12. 发明授权

US07707396B2 Data processing system, processor and method of data processing having improved branch target address cache 失效
标题翻译：数据处理系统，处理器和数据处理方法具有改进的分支目标地址缓存
公开(公告)号：US07707396B2
公开(公告)日：2010-04-27
申请号：US11561002
申请日：2006-11-17
申请人： Jeffrey P. Bradford , Richard W. Doing , Richard J. Eickemeyer , Wael R. El-Essawy , Douglas R. Logan , Balaram Sinharoy , William E. Speght , Lixin Zhang
发明人： Jeffrey P. Bradford , Richard W. Doing , Richard J. Eickemeyer , Wael R. El-Essawy , Douglas R. Logan , Balaram Sinharoy , William E. Speght , Lixin Zhang
IPC分类号： G06F9/00 , G06F9/44 , G06F7/38
CPC分类号： G06F9/3806 , G06F9/30094 , G06F9/3013 , G06F9/3017 , G06F9/384 , G06F9/3844 , G06F9/3853
摘要： A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch target address. The branch target address cache accesses the branch target buffer using a branch instruction address to obtain a predicted branch target address for use as an instruction fetch address. The branch target address cache also includes a filter buffer that buffers one or more candidate branch target address predictions. The filter buffer associates a respective confidence indication indicative of predictive accuracy with each candidate branch target address prediction. The branch target address cache promotes candidate branch target address predictions from the filter buffer to the branch target buffer based upon their respective confidence indications.
摘要翻译：处理器包括一个执行单元和指令排序逻辑，它提取用于执行的指令。指令排序逻辑包括具有分支目标缓冲器的分支目标地址高速缓存器，该分支目标缓冲器包含多个条目，每个条目将分支指令地址的至少一部分与预测的分支目标地址相关联。分支目标地址高速缓存使用分支指令地址访问分支目标缓冲器，以获得用作指令获取地址的预测分支目标地址。分支目标地址缓存还包括缓冲一个或多个候选分支目标地址预测的过滤器缓冲器。滤波器缓冲器将表示预测精度的各个置信指示与每个候选分支目标地址预测相关联。分支目标地址缓存基于它们各自的置信度指示来提高从过滤器缓冲器到分支目标缓冲器的候选分支目标地址预测。

13. 发明授权

US07558948B2 Method for providing zero overhead looping using carry chain masking 失效
标题翻译：使用进位链掩蔽提供零开销循环的方法
公开(公告)号：US07558948B2
公开(公告)日：2009-07-07
申请号：US10946465
申请日：2004-09-20
申请人： Anthony J. Bybell , Richard W. Doing , David D. Dukro
发明人： Anthony J. Bybell , Richard W. Doing , David D. Dukro
IPC分类号： G06F9/00 , G06F9/44
CPC分类号： G06F8/443
摘要： A method for reducing overhead on a loop of a plurality of instructions is disclosed. The method includes providing a carry mask, the carry mask having a first value for the loop being performed at least the particular number of times minus one and a second value for at least a last instruction of the loop being performed a last time, providing addition logic, wherein the carry mask and a current instruction address of the plurality of instructions correspond to inputs of the addition logic and determining which of the plurality of instructions is to be executed using the carry mask to provide a resultant of the addition logic based on the carry mask and the current instruction address of the plurality of instructions.
摘要翻译：公开了一种用于减少多个指令的循环上的开销的方法。所述方法包括提供进位掩码，所述进位掩码具有所述循环的第一值至少执行所述特定次数减去1，以及至少最后一次执行所述循环的最后指令的第二值，从而提供加法逻辑，其中所述多个指令的所述进位掩码和当前指令地址对应于所述加法逻辑的输入，并且使用所述进位掩码来确定所述多条指令中的哪一条指令，以基于所述加法逻辑提供所述相加逻辑的结果携带掩码和多条指令的当前指令地址。

14. 发明授权

US07644233B2 Apparatus and method for supporting simultaneous storage of trace and standard cache lines 有权
标题翻译：用于支持跟踪标准缓存行的同时存储的装置和方法
公开(公告)号：US07644233B2
公开(公告)日：2010-01-05
申请号：US11538445
申请日：2006-10-04
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/0875 , G06F12/0897 , G06F2212/6082
摘要： A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。描述了一种用于索引到缓存中并选择所需行的机制。对缓存中包含哪些行进行控制。当在标签比较步骤中匹配时，提供在轨迹线和常规线之间的选择。

15. 发明申请

US20080250207A1 DESIGN STRUCTURE FOR CACHE MAINTENANCE 审中-公开
标题翻译：高速缓存维护的设计结构
公开(公告)号：US20080250207A1
公开(公告)日：2008-10-09
申请号：US12119375
申请日：2008-05-12
申请人： GORDON T. DAVIS , Richard W. Doing , John D. Jabusch , M.V.V. Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： GORDON T. DAVIS , Richard W. Doing , John D. Jabusch , M.V.V. Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F12/00
CPC分类号： G06F9/3844 , G06F9/3808 , G06F12/0875 , G06F12/127 , G06F2212/1021 , G06F2212/1044
摘要： A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Control is exercised over which lines are contained within the cache. This invention avoids inefficiencies in the cache by removing trace lines experiencing early exits from the cache, or trace lines that are short, by maintaining a few bits of information about the accuracy of the control flow in a trace cache line and using that information in addition to the LRU (Least Recently Used) bits that maintain the recency information of a cache line, in order to make a replacement decision.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。对缓存中包含哪些行进行控制。本发明通过在跟踪高速缓存行中维护关于控制流的准确度的几位信息并且使用该信息来避免高速缓存中的低效率，通过删除经历来自缓存的早期退出的跟踪线或短路的跟踪线到保持高速缓存行的新近度信息的LRU（最近使用的）位，以便进行替换判定。

16. 发明申请

US20080235500A1 STRUCTURE FOR INSTRUCTION CACHE TRACE FORMATION 审中-公开
标题翻译：指令高速缓存追踪形成结构
公开(公告)号：US20080235500A1
公开(公告)日：2008-09-25
申请号：US12131442
申请日：2008-06-02
申请人： GORDON T. DAVIS , Richard W. Doing , John D. Jabusch , M. V.V. Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： GORDON T. DAVIS , Richard W. Doing , John D. Jabusch , M. V.V. Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F9/30
CPC分类号： G06F12/0875 , G06F9/3806 , G06F9/3808 , G06F9/3844
摘要： A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. Instruction branches are predicted taken or not taken using a highly accurate branch history table (BHT). Branches that are predicted not taken are appended to a trace buffer and the next basic block is constructed from the remaining instructions in the fetch buffer. Branches that are predicted taken flush the remaining fetch buffer and the next address is determined using a Branch Target Address Register (BTAC).
摘要翻译：体现在机器可读存储介质中的设计结构，用于至少一个设计，制造和测试用于单个统一的一级指令高速缓存的设计，其中一些行可以包含跟踪和相同同余类中的其他行的设计可以包含提供与常规高速缓存线一致的指令。使用高度精确的分支历史表（BHT）预测采取或不采用指令分支。预测未采用的分支被附加到跟踪缓冲区，并且下一个基本块是从获取缓冲区中的其余指令构建的。预测的分支将刷新剩余的获取缓冲区，并使用分支目标地址寄存器（BTAC）确定下一个地址。

17. 发明授权

US08386712B2 Structure for supporting simultaneous storage of trace and standard cache lines 失效
标题翻译：用于支持跟踪和标准缓存行同时存储的结构
公开(公告)号：US08386712B2
公开(公告)日：2013-02-26
申请号：US12116676
申请日：2008-05-07
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0864 , G06F12/0875 , G06F12/0897 , G06F2212/6082
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.
摘要翻译：体现在用于设计，制造和/或测试用于单个统一级别的一个指令高速缓存的机器可读存储介质中的设计结构，其中一些行可以包含跟踪和相同同余类中的其他行的设计可以包含一致的指令块提供常规的高速缓存线。描述了一种用于索引到缓存中并选择所需行的机制。对缓存中包含哪些行进行控制。当在标签比较步骤中匹配时，提供在轨迹线和常规线之间的选择。

18. 发明授权

US07996618B2 Apparatus and method for using branch prediction heuristics for determination of trace formation readiness 失效
公开(公告)号：US07996618B2
公开(公告)日：2011-08-09
申请号：US13016144
申请日：2011-01-28
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F Robinson , Sumedh W Sathaye , Jeffrey R Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F Robinson , Sumedh W Sathaye , Jeffrey R Summers
IPC分类号： G06F9/40 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0875 , G06F2212/6028
摘要： A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.

19. 发明申请

US20080114964A1 Apparatus and Method for Cache Maintenance 审中-公开
标题翻译：缓存维护的设备和方法
公开(公告)号：US20080114964A1
公开(公告)日：2008-05-15
申请号：US11559512
申请日：2006-11-14
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F9/305
CPC分类号： G06F12/0893 , G06F9/3808 , G06F9/3844 , G06F12/0862
摘要： A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Control is exercised over which lines are contained within the cache. This invention avoids inefficiencies in the cache by removing trace lines experiencing early exits from the cache, or trace lines that are short, by maintaining a few bits of information about the accuracy of the control flow in a trace cache line and using that information in addition to the LRU (Least Recently Used) bits that maintain the recency information of a cache line, in order to make a replacement decision.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。对缓存中包含哪些行进行控制。本发明通过在跟踪高速缓存行中维护关于控制流的准确度的几位信息并且使用该信息来避免高速缓存中的低效率，通过删除经历来自缓存的早期退出的跟踪线或短路的跟踪线到保持高速缓存行的新近度信息的LRU（最近使用的）位，以便进行替换判定。

20. 发明授权

US07934081B2 Apparatus and method for using branch prediction heuristics for determination of trace formation readiness 失效
标题翻译：使用分支预测启发式方法确定痕量形成准备的装置和方法
公开(公告)号：US07934081B2
公开(公告)日：2011-04-26
申请号：US11538831
申请日：2006-10-05
申请人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
发明人： Gordon T. Davis , Richard W. Doing , John D. Jabusch , M V V Anil Krishna , Brett Olsson , Eric F. Robinson , Sumedh W. Sathaye , Jeffrey R. Summers
IPC分类号： G06F9/40 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0875 , G06F2212/6028
摘要： A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.
摘要翻译：单个统一的一级指令高速缓存，其中一些行可以包含跟踪和同一同余类中的其他行可以包含与常规高速缓存行一致的指令块。缓存中的跟踪行的形成在系统的初始操作中被延迟，以确保存储的跟踪线的质量。

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