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11. 发明申请

US20130332713A1 FAST INDEX TREE FOR ACCELERATED BRANCH PREDICTION 有权
标题翻译：快速指数树用于加速分支预测
公开(公告)号：US20130332713A1
公开(公告)日：2013-12-12
申请号：US13494443
申请日：2012-06-12
申请人： James J. Bonanno , Brian R. Prasky , Anthony Saporito
发明人： James J. Bonanno , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3844
摘要： Embodiments relate to using a fast index tree for accelerated branch prediction. A system includes a branch target buffer, a FIT structure, and a processing circuit configured to perform a method. The method includes determining that searching of the branch target buffer is to be performed under FIT control. A current search address for searching of the branch target buffer is saved. The branch target buffer is searched at the saved current search address for a branch prediction. A FIT next-search address is determined based on reading branch taken and branch not taken paths for a next search level of predicted branches from the FIT structure. The searching of the branch target buffer is re-indexed based on the FIT next-search address. It is determined whether the searching at the saved current search address located the branch prediction.
摘要翻译：实施例涉及使用用于加速分支预测的快速索引树。系统包括分支目标缓冲器，FIT结构以及被配置为执行方法的处理电路。该方法包括确定在FIT控制下执行分支目标缓冲器的搜索。保存用于搜索分支目标缓冲器的当前搜索地址。在保存的当前搜索地址搜索分支目标缓冲区以进行分支预测。基于读取从FIT结构预测分支的下一个搜索水平的分支取出和分支未采用的路径来确定FIT下一搜索地址。基于FIT下一搜索地址重新索引分支目标缓冲区的搜索。确定在保存的当前搜索地址处的搜索是否位于分支预测。

12. 发明申请

US20090217002A1 SYSTEM AND METHOD FOR PROVIDING ASYNCHRONOUS DYNAMIC MILLICODE ENTRY PREDICTION 失效
标题翻译：用于提供异步动态MILLICODE入侵预测的系统和方法
公开(公告)号：US20090217002A1
公开(公告)日：2009-08-27
申请号：US12035109
申请日：2008-02-21
申请人： James J. Bonanno , Brian R. Prasky , John G. Rell, JR. , Anthony Saporito , Chung-Lung Kevin Shum
发明人： James J. Bonanno , Brian R. Prasky , John G. Rell, JR. , Anthony Saporito , Chung-Lung Kevin Shum
IPC分类号： G06F9/312
CPC分类号： G06F9/3017 , G06F9/30145 , G06F9/30174 , G06F9/3806
摘要： A system and method for asynchronous dynamic millicode entry prediction in a processor are provided. The system includes a branch target buffer (BTB) to hold branch information. The branch information includes: a branch type indicating that the branch represents a millicode entry (mcentry) instruction targeting a millicode subroutine, and an instruction length code (ILC) associated with the mcentry instruction. The system also includes search logic to perform a method. The method includes locating a branch address in the BTB for the mcentry instruction targeting the millicode subroutine, and determining a return address to return from the millicode subroutine as a function of the an instruction address of the mcentry instruction and the ILC. The system further includes instruction fetch controls to fetch instructions of the millicode subroutine asynchronous to the search logic. The search logic may also operate asynchronous with respect to an instruction decode unit.
摘要翻译：提供了一种用于在处理器中进行异步动态毫代码入口预测的系统和方法。该系统包括用于保存分支信息的分支目标缓冲器（BTB）。分支信息包括：分支类型，指示分支表示针对毫微米子例程的毫米条目（中心）指令，以及与中心指令相关联的指令长度代码（ILC）。该系统还包括执行方法的搜索逻辑。该方法包括将BTB中的分支地址定位到针对毫秒子程序的中心指令，以及根据中心指令和ILC的指令地址确定返回地址，以从millicode子程序返回。该系统还包括指令获取控制以获取与搜索逻辑异步的毫微数子程序的指令。搜索逻辑也可以相对于指令解码单元进行异步操作。

13. 发明申请

US20090210661A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR AN IMPLICIT PREDICTED RETURN FROM A PREDICTED SUBROUTINE 失效
标题翻译：方法，系统和计算机程序产品预测从预测的SUBROUTINE返回
公开(公告)号：US20090210661A1
公开(公告)日：2009-08-20
申请号：US12034066
申请日：2008-02-20
申请人： Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III , Charles F. Webb
发明人： Khary J. Alexander , James J. Bonanno , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III , Charles F. Webb
IPC分类号： G06F9/312
CPC分类号： G06F9/30054 , G06F9/3804 , G06F9/3806 , G06F9/3844
摘要： A method, system and computer program product for performing an implicit predicted return from a predicted subroutine are provided. The system includes a branch history table/branch target buffer (BHT/BTB) to hold branch information, including a target address of a predicted subroutine and a branch type. The system also includes instruction buffers, and instruction fetch controls to perform a method including fetching a branch instruction at a branch address and a return-point instruction. The method also includes receiving the target address and the branch type, and fetching a fixed number of instructions in response to the branch type. The method further includes referencing the return-point instruction within the instruction buffers such that the return-point instruction is available upon completing the fetching of the fixed number of instructions absent a re-fetch of the return-point instruction.
摘要翻译：提供了一种用于从预测子程序执行隐含预测返回的方法，系统和计算机程序产品。该系统包括用于保持分支信息的分支历史表/分支目标缓冲器（BHT / BTB），包括预测子程序的目标地址和分支类型。该系统还包括指令缓冲器和指令获取控制，以执行包括在分支地址和返回点指令处获取分支指令的方法。该方法还包括接收目标地址和分支类型，以及响应于分支类型取出固定数目的指令。该方法还包括引用指令缓冲器内的返回点指令，使得在没有重新获取返回点指令的情况下完成取出固定数目的指令后，返回点指令是可用的。

14. 发明申请

US20090204797A1 METHOD AND SYSTEM FOR MITIGATING LOOKAHEAD BRANCH PREDICTION LATENCY WITH BRANCH PRESENCE PREDICTION AT THE TIME OF INSTRUCTION FETCHING 有权
标题翻译：用于在指示期间缓解分支预测的预测分支预测方法和系统
公开(公告)号：US20090204797A1
公开(公告)日：2009-08-13
申请号：US12029543
申请日：2008-02-12
申请人： James J. Bonanno , David S. Hutton , Brian R. Prasky , Anthony Saporito
发明人： James J. Bonanno , David S. Hutton , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/32
CPC分类号： G06F9/3844 , G06F9/3806 , G06F9/3836 , G06F9/3848
摘要： System and method for mitigating lookahead branch prediction latency with branch presence prediction at the time of instruction fetching. An exemplary embodiment includes a method for mitigating lookahead branch prediction latency, the method including receiving an instruction address in an instruction cache for fetching instructions in the microprocessor pipeline, receiving the instruction address in a branch presence predictor coupled to the microprocessor pipeline, and releasing instructions extracted from the instruction cache after determining that a branch prediction is available or unlikely to occur for instructions identified as potential predictable branches by the branch presence prediction.
摘要翻译：用于在指令获取时用分支存在预测来减轻前瞻分支预测延迟的系统和方法。一个示例性实施例包括一种用于减轻前瞻分支预测等待时间的方法，所述方法包括：在指令高速缓存中接收指令地址以获取微处理器流水线中的指令，在耦合到微处理器流水线的分支存在预测器中接收指令地址，以及释放指令在通过分支存在预测识别为潜在可预测分支的指令之后，在确定分支预测可用或不太可能发生之后从指令高速缓存提取。

15. 发明授权

US09250912B2 Fast index tree for accelerated branch prediction 有权
标题翻译：用于加速分支预测的快速索引树
公开(公告)号：US09250912B2
公开(公告)日：2016-02-02
申请号：US13494443
申请日：2012-06-12
申请人： James J. Bonanno , Brian R. Prasky , Anthony Saporito
发明人： James J. Bonanno , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/3806 , G06F9/3844
摘要： Embodiments relate to using a fast index tree for accelerated branch prediction. A system includes a branch target buffer, a FIT structure, and a processing circuit configured to perform a method. The method includes determining that searching of the branch target buffer is to be performed under FIT control. A current search address for searching of the branch target buffer is saved. The branch target buffer is searched at the saved current search address for a branch prediction. A FIT next-search address is determined based on reading branch taken and branch not taken paths for a next search level of predicted branches from the FIT structure. The searching of the branch target buffer is re-indexed based on the FIT next-search address. It is determined whether the searching at the saved current search address located the branch prediction.
摘要翻译：实施例涉及使用用于加速分支预测的快速索引树。系统包括分支目标缓冲器，FIT结构以及被配置为执行方法的处理电路。该方法包括确定在FIT控制下执行分支目标缓冲器的搜索。保存用于搜索分支目标缓冲器的当前搜索地址。在保存的当前搜索地址搜索分支目标缓冲区以进行分支预测。基于读取从FIT结构预测分支的下一个搜索水平的分支取出和分支未采用的路径来确定FIT下一搜索地址。基于FIT下一搜索地址重新索引分支目标缓冲区的搜索。确定在保存的当前搜索地址处的搜索是否位于分支预测。

16. 发明授权

US08443176B2 Method, system, and computer program product for reducing cache memory pollution 有权
标题翻译：方法，系统和计算机程序产品，用于减少缓存内存污染
公开(公告)号：US08443176B2
公开(公告)日：2013-05-14
申请号：US12037042
申请日：2008-02-25
申请人： Robert J. Sonnelitter, III , James J. Bonanno , David S. Hutton , Brian R. Prasky , Anthony Saporito
发明人： Robert J. Sonnelitter, III , James J. Bonanno , David S. Hutton , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/00
CPC分类号： G06F9/3804 , G06F9/30058 , G06F12/0862 , G06F2212/1021
摘要： A method for reducing cache memory pollution including fetching an instruction stream from a cache line, preventing a fetching for the instruction stream from a sequential cache line, searching for a next predicted taken branch instruction, determining whether a length of the instruction stream extends beyond a length of the cache line based on the next predicted taken branch instruction, continuing preventing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream does not extend beyond the length of the cache line, and allowing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream extends beyond the length of the cache line, whereby the fetching from the sequential cache line and a resulting polluting of a cache memory that stores the instruction stream is minimized. A corresponding system and computer program product.
摘要翻译：一种用于减少高速缓冲存储器污染的方法，包括从高速缓存线取出指令流，阻止从顺序高速缓存线取出指令流，搜索下一个预测的分支指令，确定指令流的长度是否延伸超过基于下一个预测的分支指令的高速缓存线的长度，如果指令流的长度不超过高速缓存线的长度，则继续阻止从顺序高速缓存行获取指令流，并且允许取出如果指令流的长度延伸超过高速缓存行的长度，则来自顺序高速缓存行的指令流被最小化，从而从顺序高速缓存行的取出和存储指令流的高速缓冲存储器的产生的污染最小化。相应的系统和计算机程序产品。

17. 发明申请

US20090217003A1 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR REDUCING CACHE MEMORY POLLUTION 有权
标题翻译：用于减少高速缓存存储器污染的方法，系统和计算机程序产品
公开(公告)号：US20090217003A1
公开(公告)日：2009-08-27
申请号：US12037042
申请日：2008-02-25
申请人： Robert J. Sonnelitter, III , James J. Bonanno , David S. Hutton , Brian R. Prasky , Anthony Saporito
发明人： Robert J. Sonnelitter, III , James J. Bonanno , David S. Hutton , Brian R. Prasky , Anthony Saporito
IPC分类号： G06F9/30
CPC分类号： G06F9/3804 , G06F9/30058 , G06F12/0862 , G06F2212/1021
摘要： A method for reducing cache memory pollution including fetching an instruction stream from a cache line, preventing a fetching for the instruction stream from a sequential cache line, searching for a next predicted taken branch instruction, determining whether a length of the instruction stream extends beyond a length of the cache line based on the next predicted taken branch instruction, continuing preventing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream does not extend beyond the length of the cache line, and allowing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream extends beyond the length of the cache line, whereby the fetching from the sequential cache line and a resulting polluting of a cache memory that stores the instruction stream is minimized. A corresponding system and computer program product.
摘要翻译：一种用于减少高速缓冲存储器污染的方法，包括从高速缓存线取出指令流，阻止从顺序高速缓存线取出指令流，搜索下一个预测的分支指令，确定指令流的长度是否延伸超过基于下一个预测的分支指令的高速缓存线的长度，如果指令流的长度不超过高速缓存线的长度，则继续阻止从顺序高速缓存行获取指令流，并且允许取出如果指令流的长度延伸超过高速缓存行的长度，则来自顺序高速缓存行的指令流被最小化，从而从顺序高速缓存行的取出和存储指令流的高速缓冲存储器的产生的污染最小化。相应的系统和计算机程序产品。

18. 发明授权

US08972665B2 Cache set selective power up 有权
标题翻译：缓存设置选择上电
公开(公告)号：US08972665B2
公开(公告)日：2015-03-03
申请号：US13524574
申请日：2012-06-15
申请人： Brian R. Prasky , Anthony Saporito , Aaron Tsai
发明人： Brian R. Prasky , Anthony Saporito , Aaron Tsai
IPC分类号： G06F1/32 , G06F21/81 , G06F17/30
CPC分类号： G06F1/3275 , G06F9/3802 , G06F12/0864 , G06F17/30982 , G06F2212/1028 , G06F2212/6082 , Y02D10/13
摘要： Embodiments of the disclosure include selectively powering up a cache set of a multi-set associative cache by receiving an instruction fetch address and determining that the instruction fetch address corresponds to one of a plurality of entries of a content addressable memory. Based on determining that the instruction fetch address corresponds to one of a plurality of entries of a content addressable memory a cache set of the multi-set associative cache that contains a cache line referenced by the instruction fetch address is identified and only powering up a subset of cache. Based on the identified cache set not being powered up, selectively powering up the identified cache set of the multi-set associative cache and transmitting one or more instructions stored in the cache line referenced by the instruction fetch address to a processor.
摘要翻译：本公开的实施例包括通过接收指令获取地址并且确定指令获取地址对应于内容可寻址存储器的多个条目之一来选择性地加电多组关联高速缓存的高速缓存组。基于确定指令获取地址对应于内容可寻址存储器的多个条目中的一个，识别包含由指令获取地址引用的高速缓存行的多组关联高速缓存的高速缓存集，并且仅为子集的缓存。基于所识别的未被加电的高速缓存集，选择性地加电多组关联高速缓存的所识别的高速缓存集，并且将由指令提取地址引用的高速缓存行中存储的一个或多个指令发送到处理器。

19. 发明授权

US09021240B2 System and method for Controlling restarting of instruction fetching using speculative address computations 有权
标题翻译：使用推测地址计算控制指令重写的系统和方法
公开(公告)号：US09021240B2
公开(公告)日：2015-04-28
申请号：US12035911
申请日：2008-02-22
申请人： Khary J. Alexander , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III
发明人： Khary J. Alexander , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III
IPC分类号： G06F9/38 , G06F9/32
CPC分类号： G06F9/3861 , G06F9/322 , G06F9/3804 , G06F9/3806 , G06F9/3838 , G06F9/3842 , G06F9/3867
摘要： A system and method for controlling restarting of instruction fetching using speculative address computations in a processor are provided. The system includes a predicted target queue to hold branch prediction logic (BPL) generated target address values. The system also includes target selection logic including a recycle queue. The target selection logic selects a saved branch target value between a previously speculatively calculated branch target value from the recycle queue and an address value from the predicted target queue. The system further includes a compare block to identify a wrong target in response to a mismatch between the saved branch target value and a current calculated branch target, where instruction fetching is restarted in response to the wrong target.
摘要翻译：提供了一种用于使用处理器中的推测地址计算来控制重新启动指令取出的系统和方法。该系统包括预测的目标队列以保持分支预测逻辑（BPL）生成的目标地址值。系统还包括目标选择逻辑，包括循环队列。目标选择逻辑从先前推测计算出的来自再循环队列的分支目标值和来自预测目标队列的地址值之间选择保存的分支目标值。系统还包括比较块，用于响应于所保存的分支目标值与当前计算的分支目标之间的不匹配来识别错误的目标，其中响应于错误的目标重新启动指令获取。

20. 发明申请

US20090217017A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MINIMIZING BRANCH PREDICTION LATENCY 审中-公开
标题翻译：用于最小化分支预测延迟的方法，系统和计算机程序产品
公开(公告)号：US20090217017A1
公开(公告)日：2009-08-27
申请号：US12037137
申请日：2008-02-26
申请人： Khary J. Alexander , David S. Hutton , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III , John W. Ward, III
发明人： Khary J. Alexander , David S. Hutton , Brian R. Prasky , Anthony Saporito , Robert J. Sonnelitter, III , John W. Ward, III
IPC分类号： G06F9/30
CPC分类号： G06F9/381 , G06F9/3806 , G06F9/3814
摘要： A method, system, and computer program product for minimizing branch prediction latency in a pipelined computer processing environment are provided. The method includes detecting a branch loop utilizing branch instruction addresses and corresponding target addresses stored in a branch target buffer (BTB). The method also includes fetching the branch loop into a pre-decode instruction buffer and qualifying the branch loop for loop lockdown. The method further includes locking an instruction stream that forms the branch loop in the pre-decode instruction buffer and processing qualified branch loop instructions from the buffer and powering down instruction fetching and branch prediction logic (BPL) associated with the BTB.
摘要翻译：提供了一种用于在流水线计算机处理环境中最小化分支预测延迟的方法，系统和计算机程序产品。该方法包括利用转移指令地址和存储在分支目标缓冲器（BTB）中的对应目标地址来检测分支回路。该方法还包括将分支循环读取到预解码指令缓冲器中，并对分支循环进行限定循环锁定。该方法还包括将形成分支循环的指令流锁定在预解码指令缓冲器中，并且处理来自缓冲器的限定分支循环指令并且断电与BTB相关联的指令获取和分支预测逻辑（BPL）。

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