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11. 发明申请

US20070257376A1 SEMICONDUCTOR MODULE 审中-公开
公开(公告)号：US20070257376A1
公开(公告)日：2007-11-08
申请号：US11778493
申请日：2007-07-16
申请人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
发明人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
IPC分类号： H01L23/48
CPC分类号： H01L23/3121 , H01L21/565 , H01L23/36 , H01L23/367 , H01L23/4822 , H01L23/49805 , H01L23/49844 , H01L24/16 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/84 , H01L25/0655 , H01L25/165 , H01L29/4175 , H01L29/7802 , H01L29/7806 , H01L29/7809 , H01L29/7813 , H01L29/7835 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40225 , H01L2224/73153 , H01L2224/73204 , H01L2224/73253 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.

12. 发明申请

US20060055432A1 Semiconductor module 失效
公开(公告)号：US20060055432A1
公开(公告)日：2006-03-16
申请号：US11214730
申请日：2005-08-31
申请人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
发明人： Kazuo Shimokawa , Takashi Koyanagawa , Masako Ooishi , Tatsuya Yamada , Osamu Usuda , Yoshiki Endo , Taiki Miura , Masaki Toyoshima , Ichiro Omura , Akio Nakagawa , Kenichi Matsushita , Yusuke Kawaguchi , Haruki Arai , Hiroshi Takei , Tomohiro Kawano , Noriaki Yoshikawa , Morio Takahashi , Yasuhito Saito , Masahiro Urase
IPC分类号： H03D13/00
CPC分类号： H01L23/3121 , H01L21/565 , H01L23/36 , H01L23/367 , H01L23/4822 , H01L23/49805 , H01L23/49844 , H01L24/16 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/84 , H01L25/0655 , H01L25/165 , H01L29/4175 , H01L29/7802 , H01L29/7806 , H01L29/7809 , H01L29/7813 , H01L29/7835 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40225 , H01L2224/73153 , H01L2224/73204 , H01L2224/73253 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor module comprises a mounting board. A plurality of power switching device chips are mounted on the mounting board by flip-chip bonding. The chip has an upper surface and a lower surface and is configured to face the upper surface toward the mounting board. A drive IC chip is mounted on the mounting board by flip-chip bonding. The drive IC chip is operative to drive gates of transistors formed in the plurality of power switching device chips. A plurality of heat sink members are located on the lower surfaces of the plurality of power switching device chips, respectively. A resinous member is provided to seal the plurality of power switching device chips and the drive IC chip in a single package.

13. 发明申请

US20110042715A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110042715A1
公开(公告)日：2011-02-24
申请号：US12917614
申请日：2010-11-02
申请人： Masanori Tsukuda , Ichiro Omura
发明人： Masanori Tsukuda , Ichiro Omura
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0661 , H01L29/0696 , H01L29/0834 , H01L29/66348
摘要： A semiconductor device includes a semiconductor substrate; a first base region of a first conductivity type provided in the semiconductor substrate; a buffer region of the first conductivity type provided on a lower surface of the first base region and having an impurity concentration higher than an impurity concentration of the first base region; an emitter region of a second conductivity type provided on a lower surface of the buffer region; a second base region of the second conductivity type selectively provided on an upper surface of the first base region; a diffusion region of the first conductivity type selectively provided on an upper surface of the second base region; a control electrode; a first main electrode; and a second main electrode. A junction interface between the buffer region and the first base region has a concave portion and a convex portion.
摘要翻译：半导体器件包括半导体衬底; 设置在半导体衬底中的第一导电类型的第一基极区域; 所述第一导电类型的缓冲区域设置在所述第一基极区域的下表面上，并且具有高于所述第一基极区域的杂质浓度的杂质浓度; 设置在所述缓冲区域的下表面上的第二导电类型的发射极区域; 所述第二导电类型的第二基极区域选择性地设置在所述第一基极区域的上表面上; 所述第一导电类型的扩散区域选择性地设置在所述第二基极区域的上表面上; 控制电极; 第一主电极; 和第二主电极。缓冲区域和第一基底区域之间的结界面具有凹部和凸部。

14. 发明申请

US20090206365A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20090206365A1
公开(公告)日：2009-08-20
申请号：US12368573
申请日：2009-02-10
申请人： Masanori Tsukuda , Ichiro Omura
发明人： Masanori Tsukuda , Ichiro Omura
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0661 , H01L29/0696 , H01L29/0834 , H01L29/66348
摘要： A semiconductor device includes a semiconductor substrate; a first base region of a first conductivity type provided in the semiconductor substrate; a buffer region of the first conductivity type provided on a lower surface of the first base region and having an impurity concentration higher than an impurity concentration of the first base region; an emitter region of a second conductivity type provided on a lower surface of the buffer region; a second base region of the second conductivity type selectively provided on an upper surface of the first base region; a diffusion region of the first conductivity type selectively provided on an upper surface of the second base region; a control electrode; a first main electrode; and a second main electrode. A junction interface between the buffer region and the first base region has a concave portion and a convex portion.
摘要翻译：半导体器件包括半导体衬底; 设置在半导体衬底中的第一导电类型的第一基极区域; 所述第一导电类型的缓冲区域设置在所述第一基极区域的下表面上，并且具有高于所述第一基极区域的杂质浓度的杂质浓度; 设置在缓冲区域的下表面上的第二导电类型的发射极区域; 所述第二导电类型的第二基极区域选择性地设置在所述第一基极区域的上表面上; 所述第一导电类型的扩散区域选择性地设置在所述第二基极区域的上表面上; 控制电极; 第一主电极; 和第二主电极。缓冲区域和第一基底区域之间的结界面具有凹部和凸部。

15. 发明授权

US07508015B2 Semiconductor device using a nitride semiconductor 有权
标题翻译：使用氮化物半导体的半导体装置
公开(公告)号：US07508015B2
公开(公告)日：2009-03-24
申请号：US11354148
申请日：2006-02-15
申请人： Wataru Saito , Ichiro Omura
发明人： Wataru Saito , Ichiro Omura
IPC分类号： H01L31/0328
CPC分类号： H01L29/432 , H01L29/1066 , H01L29/2003 , H01L29/402 , H01L29/4236 , H01L29/7786 , H01L29/7787
摘要： A semiconductor device includes: a first semiconductor layer represented by a composition formula AlxGa1-xN (0≦x≦1); a first conductivity type or non-doped second semiconductor layer represented by a composition formula AlyGa1-yN (0≦y≦1, x
摘要翻译：半导体器件包括：由组成式Al x Ga 1-x N（0≤x≤1）表示的第一半导体层; 由第一半导体层形成的由组成式AlyGa1-yN（0≤y≤1，x

16. 发明授权

US07459945B2 Gate driving circuit and gate driving method of power MOSFET 失效
标题翻译：功率MOSFET的栅极驱动电路和栅极驱动方法
公开(公告)号：US07459945B2
公开(公告)日：2008-12-02
申请号：US11189704
申请日：2005-07-27
申请人： Ichiro Omura
发明人： Ichiro Omura
IPC分类号： H03K3/00
CPC分类号： H03K17/04123 , H03K17/6877
摘要： A gate driving circuit and method which increases the switching frequency by use of a switching control circuit which controls operations of a first, second, third, and fourth switches. The switching control circuit performs switching control of a power MOSFET when the MOSFET is to be turned on, so that a period exists when the first and fourth switches are simultaneously ON. The switching circuit also performs switching control when a MOSFET is to be turned off, so that a period exists when the second and third switches are simultaneously ON.
摘要翻译：一种通过使用控制第一，第二，第三和第四开关的操作的开关控制电路来提高开关频率的栅极驱动电路和方法。当MOSFET接通时，开关控制电路执行功率MOSFET的开关控制，从而当第一和第四开关同时导通时，存在周期。当MOSFET关闭时，开关电路还执行开关控制，从而当第二和第三开关同时接通时，存在周期。

17. 发明申请

US20070241337A1 NITRIDE SEMICONDUCTOR DEVICE 失效
标题翻译：氮化物半导体器件
公开(公告)号：US20070241337A1
公开(公告)日：2007-10-18
申请号：US11766484
申请日：2007-06-21
申请人： Wataru Saito , Ichiro Omura
发明人： Wataru Saito , Ichiro Omura
IPC分类号： H01L29/94
CPC分类号： H01L29/66462 , H01L29/0692 , H01L29/1066 , H01L29/2003 , H01L29/7786
摘要： In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an undoped or n-type aluminum gallium nitride (AlGaN) layer serving as a barrier layer.
摘要翻译：在根据本发明的一个实施方案的氮化物半导体器件中，在未掺杂的或未掺杂的或未掺杂的氮化物半导体器件上形成电连接到源电极并相对于栅电极延伸并突出到漏极侧的p型氮化镓（GaN） n型氮化镓铝（AlGaN）层作为阻挡层。

18. 发明授权

US07276773B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US07276773B2
公开(公告)日：2007-10-02
申请号：US11117342
申请日：2005-04-29
申请人： Wataru Saito , Ichiro Omura
发明人： Wataru Saito , Ichiro Omura
IPC分类号： H01L29/72
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0878 , H01L29/7397 , H01L29/872
摘要： A power semiconductor device includes second semiconductor layers of a first conductivity type and third semiconductor layers of a second conductivity type alternately disposed on a first semiconductor layer of the first conductivity type. The device further includes fourth semiconductor layers of the second conductivity type disposed in contact with upper portions of the third semiconductor layers between the second semiconductor layers, and fifth semiconductor layers of the first conductivity type formed in surfaces of the fourth semiconductor layers. The first semiconductor layer is lower in impurity concentration of the first conductivity type than each second semiconductor layer. The third semiconductor layer includes a fundamental portion and an impurity-amount-larger portion formed locally in a depth direction and higher in impurity amount than the fundamental portion. The impurity amount is defined by a total amount of impurities of the second conductivity type over a cross section in a lateral direction.
摘要翻译：功率半导体器件包括交替设置在第一导电类型的第一半导体层上的第一导电类型的第二半导体层和第二导电类型的第三半导体层。该器件还包括第二导电类型的第四半导体层，与第二半导体层之间的第三半导体层的上部接触，以及形成在第四半导体层的表面中的第一导电类型的第五半导体层。第一半导体层的第一导电类型的杂质浓度比每个第二半导体层低。第三半导体层包括基本部分和在深度方向上局部形成的杂质量较大部分，并且杂质量高于基本部分。杂质量由横向横截面上的第二导电类型的杂质的总量限定。

19. 发明申请

US20070114602A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20070114602A1
公开(公告)日：2007-05-24
申请号：US11562708
申请日：2006-11-22
申请人： Wataru Saito , Ichiro Omura
发明人： Wataru Saito , Ichiro Omura
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0615 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/66734 , H01L29/7397 , H01L29/7811
摘要： A semiconductor device includes: a first semiconductor layer of a first conductivity type; a first semiconductor region of the first conductivity type and a second semiconductor region of a second conductivity type alternately arranged in a lateral direction on the first semiconductor layer of the first conductivity type; a third semiconductor region of the second conductivity type formed on the first semiconductor region; a fourth semiconductor region of the first conductivity type formed on a portion of the surface of the third semiconductor region; a control electrode provided via an first insulating film in a groove formed in contact with the fourth semiconductor region, the third semiconductor region, and the first semiconductor region; a first main electrode electrically connected to the first semiconductor layer; a second main electrode forming a junction with the third and fourth semiconductor region; and a fifth semiconductor region of the second conductivity type. The fifth semiconductor region is formed in contact with the first insulating film, the first semiconductor region, and the second semiconductor region. The bottom face of the fifth semiconductor region is deeper than the bottom face of the control electrode. Alternatively, the fifth semiconductor region may be spaced apart from the first insulating film.
摘要翻译：半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第一半导体区域和在第一导电类型的第一半导体层上沿横向交替布置的第二导电类型的第二半导体区域; 形成在第一半导体区域上的第二导电类型的第三半导体区域; 形成在第三半导体区域的表面的一部分上的第一导电类型的第四半导体区域; 在与所述第四半导体区域，所述第三半导体区域和所述第一半导体区域接触形成的沟槽中经由第一绝缘膜设置的控制电极; 电连接到第一半导体层的第一主电极; 形成与第三和第四半导体区域的结的第二主电极; 和第二导电类型的第五半导体区域。第五半导体区域形成为与第一绝缘膜，第一半导体区域和第二半导体区域接触。第五半导体区域的底面比控制电极的底面更深。或者，第五半导体区域可以与第一绝缘膜间隔开。

20. 发明申请

US20060170003A1 Nitride semiconductor device 失效
标题翻译：氮化物半导体器件
公开(公告)号：US20060170003A1
公开(公告)日：2006-08-03
申请号：US11149208
申请日：2005-06-10
申请人： Wataru Saito , Ichiro Omura , Kouhei Morizuka
发明人： Wataru Saito , Ichiro Omura , Kouhei Morizuka
IPC分类号： H01L31/109
CPC分类号： H01L29/7787 , H01L29/0649 , H01L29/1608 , H01L29/2003 , H01L29/267 , H01L29/402 , H01L29/4175 , H01L29/66462
摘要： A multi-layered structure in which a p-3C-SiC layer 102 is formed above a p-Si substrate 101 is formed, above which an I-GaN layer (channel layer) 103, an n-AlGaN layer (barrier layer) 104 are formed. A source electrode 201, a drain electrode 202, and a gate electrode 203 are formed above the n-AlGaN layer 104. The source electrode 201 and the drain electrode 202 form an ohmic contact with the n-AlGaN layer 104. The gate electrode 203 forms a Schottky junction with the n-AlGaN layer 104.
摘要翻译：形成在p-Si衬底101上形成p-3C-SiC层102的多层结构，其中I-GaN层（沟道层）103，n-AlGaN层（势垒层）104 形成。源极电极201，漏极电极202和栅电极203形成在n-AlGaN层104的上方。源电极201和漏电极202与n-AlGaN层104形成欧姆接触。栅电极203与n-AlGaN层104形成肖特基结。

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