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11. 发明申请

WO2021062243A2 SYSTEMS, METHODS, AND APPARATUS FOR SOFTWARE DEFINED SILICON SECURITY 审中-公开
公开(公告)号：WO2021062243A2
公开(公告)日：2021-04-01
申请号：PCT/US2020/052848
申请日：2020-09-25
申请人： INTEL CORPORATION
发明人： BARTFAI-WALCOTT, Katalin Klara , BERENT, Arkadiusz , CHILUKURI, Vasuki , BALDWIN, Mark , SRINIVASAN, Vasudevan , SEHGAL, Naresh , NOVICK, David , GOTOWALSKI, Bartosz
IPC分类号： G06Q50/04 , G06F21/10 , G06Q30/00 , G06Q30/06 , G06F11/3058 , G06F21/105 , G06F21/445 , G06F21/602 , G06F9/44505 , H04L9/0866 , H04L9/3278
摘要： Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) for software defined silicon security are disclosed. Example apparatus include a trusted agent determiner to (i) determine respective reputation scores associated with a plurality of agents in a mesh network, the plurality of agents associated with a plurality of semiconductor devices, respective ones of the semiconductor devices including circuitry configurable to provide one or more features, and (ii) select, based on the respective reputation scores, a first agent from the plurality of the agents to transmit a request to activate or deactivate at least one of the one or more features. Example apparatus also include an agent interface to, in response to the request, broadcast an activation or deactivation of the least one of the one or more features to the mesh network to cause the trusted agent determiner to update the reputation score of the first agent.

12. 发明申请

WO2021062242A1 SOFTWARE DEFINED SILICON IMPLEMENTATION AND MANAGEMENT 审中-公开
公开(公告)号：WO2021062242A1
公开(公告)日：2021-04-01
申请号：PCT/US2020/052847
申请日：2020-09-25
申请人： INTEL CORPORATION
发明人： BARTFAI-WALCOTT, Katalin Klara , BERENT, Arkadiusz , CHILUKURI, Vasuki , BALDWIN, Mark , SRINIVASAN, Vasudevan , ROSE, Vinila , ORIOL, Mariusz , CHILCZUK, Justyna , GOTOWALSKI, Bartosz
IPC分类号： G06Q50/04 , G06Q30/00 , G06Q30/06 , G06F21/10
摘要： Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement and manage software defined silicon products are disclosed. Example semiconductor devices disclosed herein include circuitry configurable to provide one or more features. Disclosed example semiconductor devices also include a license processor to activate or deactivate at least one of the one or more features based on a license received via a network from a first remote enterprise system. Disclosed example semiconductor devices further include an analytics engine to report telemetry data associated with operation of the semiconductor device to at least one of the first remote enterprise system or a second remote enterprise system, the analytics engine to report the telemetry data in response to activation or deactivation of the at least one of the one or more features based on the license.

13. 发明申请

WO2018063553A1 SHARING OF ENVIRONMENTAL DATA FOR CLIENT DEVICE USAGE 审中-公开
标题翻译：为客户端设备使用共享环境数据
公开(公告)号：WO2018063553A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/047187
申请日：2017-08-16
申请人： INTEL CORPORATION
发明人： SRINIVASAN, Vasudevan , COOPER, Barnes , RAHAL-ARABI, Tawfik M.
IPC分类号： H04L29/08 , H04L29/06 , H04W4/00
摘要： Embodiments are generally directed to sharing of environmental data for client device usage. An embodiment of a client device includes a processor; an environmental sensor to sense an environmental condition, an output of the sensor being a local environmental sensor value; and a wireless receiver to receive environmental data for a certain proximity area from a second client device according to an environmental data sharing protocol via a wireless network. The environmental data sharing protocol allows receipt of the environmental data without requiring pairing, bonding, or other relationship of client devices.
摘要翻译：实施例通常针对共享用于客户端设备使用的环境数据。客户端设备的实施例包括处理器; 感测环境条件的环境传感器，所述传感器的输出是本地环境传感器值; 以及无线接收器，用于经由无线网络根据环境数据共享协议从第二客户端设备接收用于特定接近区域的环境数据。环境数据共享协议允许接收环境数据，而不需要配对，绑定或客户端设备的其他关系。

14. 发明申请

WO2016133664A1 PERFORMING DYNAMIC POWER CONTROL OF PLATFORM DEVICES 审中-公开
标题翻译：执行平台设备的动态功率控制
公开(公告)号：WO2016133664A1
公开(公告)日：2016-08-25
申请号：PCT/US2016/015075
申请日：2016-01-27
申请人： INTEL CORPORATION
发明人： VARMA, Ankush , SISTLA, Krishnakanth V. , SRINIVASAN, Vasudevan , GORBATOV, Eugene , HENROID, Andrew D. , COOPER, Barnes , BROWNING, David W. , THERIEN, Guy M. , SONGER, Neil W. , HERMERDING II, James G.
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3206 , G06F1/3203 , G06F1/3287 , G06F9/50 , Y02B70/126 , Y02D10/171
摘要： In one embodiment, a processor includes at least one core to execute instructions and a power control logic to receive power capability information from a plurality of devices to couple to the processor and allocate a platform power budget to the devices, set a first power level for the devices at which the corresponding device is allocated to be powered, communicate the first power level to the devices, and dynamically reduce a first power to be allocated to a first device and increase a second power to be allocated to a second device responsive to a request from the second device for a higher power level. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括执行指令的至少一个核心和用于从多个设备接收功率能力信息的功率控制逻辑以耦合到处理器并且向设备分配平台功率预算，为分配相应设备被供电的设备将第一功率电平传送到设备，并且动态地减少要分配给第一设备的第一功率并且增加要分配给第二设备的第二功率，以响应于来自第二设备的更高功率电平的请求。描述和要求保护其他实施例。

15. 发明公开

EP3382500A1 THROTTLING, SUB-NODE COMPOSITION, AND BALANCED PROCESSING IN RACK SCALE ARCHITECTURE 无效
公开(公告)号：EP3382500A1
公开(公告)日：2018-10-03
申请号：EP18154432.1
申请日：2018-01-31
申请人： Intel Corporation
发明人： KUMAR, Mohan J. , NACHIMUTHU, Murugasamy K. , SRINIVASAN, Vasudevan
IPC分类号： G06F1/20 , G06F1/30 , G06F11/30 , G06F1/32 , G06F1/28
CPC分类号： H04L47/2425 , G06F1/206 , G06F1/28 , G06F1/30 , G06F1/3206 , G06F1/324 , G06F1/3296 , G06F9/5044 , G06F9/5094 , G06F11/3058 , H04L41/5022 , H04L47/805 , H04L67/1008 , H04L67/12 , Y02D10/126 , Y02D10/172
摘要： A rack system including a plurality of nodes can implement thermal/power throttling, sub-node composition, and processing balancing based on voltage/frequency. In the thermal/power throttling, at least one resource is throttled, based at least in part on a heat event or a power event. In the sub-node composition, a plurality of computing cores is divided into a target number of domains. In the processing balancing based on voltage/frequency, a first core performs a first processing job at a first voltage or frequency, and a second core performs a second processing job at a second voltage or frequency different from the first voltage or frequency.

16. 发明申请

WO2019190683A1 SYSTEM, APPARATUS AND METHOD FOR CONTROLLABLE PROCESSOR CONFIGURATION BASED ON A TEMPERATURE SPECIFICATION 审中-公开
公开(公告)号：WO2019190683A1
公开(公告)日：2019-10-03
申请号：PCT/US2019/019946
申请日：2019-02-28
申请人： INTEL CORPORATION
发明人： AHUJA, Sandeep , GUPTA, Nikhil , SRINIVASAN, Vasudevan
IPC分类号： G06F1/20 , G06F1/32
摘要： In one embodiment, a processor includes a non-volatile storage to store a plurality of configurations for the processor, the non-volatile storage including a plurality of entries to store configuration information for the processor for one of the plurality of configurations, the configuration information including at least one of a guaranteed operating frequency and a core count, at least one of the entries to store the core count. The processor further includes a power controller to control the processor to operate at one of the plurality of configurations based at least in part on a selected thermal set point of a plurality of thermal set points of the processor, each of the plurality of thermal set points associated with one of the configurations. Other embodiments are described and claimed.

17. 发明申请

WO2018156153A1 CONFIGURATION OF BASE CLOCK FREQUENCY OF PROCESSOR BASED ON USAGE PARAMETERS 审中-公开
公开(公告)号：WO2018156153A1
公开(公告)日：2018-08-30
申请号：PCT/US2017/019484
申请日：2017-02-24
申请人： INTEL CORPORATION
发明人： SRINIVASAN, Vasudevan , SISTLA, Krishnakanth V. , GOUGH, Corey D. , STEINER, Ian M. , GUPTA, Nikhil , GARG, Vivek , VARMA, Ankush , VORA, Sujal A. , LERNER, David P. , SULLIVAN, Joseph M. , GURUMOORTHY , Nagasubramanian , BOWHILL, William J. , RAMAMURTHY , Venkatesh , MACNAMARA, Chris , BROWNE, John J. , DAS, Ripan
IPC分类号： G06F1/32 , G06F1/08 , G06F9/50
摘要： A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

18. 发明申请

WO2018063686A1 SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING LATE FUSING OF PROCESSOR FEATURES USING A NON-VOLATILE MEMORY 审中-公开
标题翻译：用于使用非易失性存储器实现处理器特征的晚期融合的系统，方法和设备
公开(公告)号：WO2018063686A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/049224
申请日：2017-08-29
申请人： INTEL CORPORATION
发明人： SRINIVASAN, Vasudevan , BORKOWSKI, Daniel G.
IPC分类号： H01L25/16 , H01L25/18 , H01L23/66 , H01L27/115
CPC分类号： H01L23/5385 , G06F1/26 , G06F9/4401 , G06F12/0246 , H01L25/18
摘要： In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing late fusing of processor features using a non-volatile memory. For instance, there is disclosed in accordance with one embodiment a functional semiconductor package, including: a processor core configurable via a plurality of configuration registers; a non-volatile storage, in which a first portion of the non-volatile storage includes permanently lockable storage that once written cannot be overwritten or modified, and in which a second portion of the non-volatile storage includes the plurality of configuration registers; a first write interface to the non-volatile storage, in which the permanently lockable storage of the non-volatile storage is wirelessly writable externally from the functional semiconductor package via the first write interface; a second write interface to the non-volatile storage through which the plurality of configuration registers are writable; configuration data for the processor core written wirelessly into the permanently lockable storage of the non-volatile storage; and in which the configuration data is distributed into the plurality of configuration registers via the second write interface at every boot of the functional semiconductor package. Other related embodiments are disclosed.
摘要翻译：根据所公开的实施例，提供了用于使用非易失性存储器来实现处理器特征的后期融合的系统，方法和设备。例如，根据一个实施例公开了一种功能半导体封装，包括：可通过多个配置寄存器配置的处理器内核; 非易失性存储装置，其中非易失性存储装置的第一部分包括永久可锁定的存储装置，该永久可锁定的存储装置一旦被写入就不能被重写或修改，并且其中非易失性存储装置的第二部分包括多个配置寄存器; 至非易失性存储器的第一写入接口，其中非易失性存储器的永久可锁定存储器经由第一写入接口从功能半导体封装体外部无线写入; 到所述非易失性存储器的第二写入接口，通过所述第二写入接口所述多个配置寄存器是可写的; 处理器核心的配置数据无线地写入非易失性存储器的永久可锁定存储器中; 并且其中在功能半导体封装的每次启动时通过第二写入接口将配置数据分配到多个配置寄存器中。披露了其他相关的实施例。

19. 发明公开

EP3776141A1 SYSTEM, APPARATUS AND METHOD FOR CONTROLLABLE PROCESSOR CONFIGURATION BASED ON A TEMPERATURE SPECIFICATION 审中-公开
公开(公告)号：EP3776141A1
公开(公告)日：2021-02-17
申请号：EP19774918.7
申请日：2019-02-28
申请人： INTEL Corporation
发明人： AHUJA, Sandeep , GUPTA, Nikhil , SRINIVASAN, Vasudevan
IPC分类号： G06F1/20 , G06F1/32

20. 发明申请

WO2022240905A1 LICENSE MANAGEMENT FOR SOFTWARE DEFINED SILICON 审中-公开
公开(公告)号：WO2022240905A1
公开(公告)日：2022-11-17
申请号：PCT/US2022/028632
申请日：2022-05-10
申请人： INTEL CORPORATION
发明人： BARTFAI-WALCOTT, Katalin , ORIOL, Mariusz , SRINIVASAN, Vasudevan , IRELAN, Peggy , STEPKA, Mariusz , MURPHY, Kaitlin , PILLILLI, Bharat , BALDWIN, Mark , BRONK, Mateusz , KARIM, Fariaz , BERENT, Arkadiusz , CHILUKURI, Vasuki
IPC分类号： G06F21/53 , G06F9/455 , G06F9/50 , G06F21/60 , G06F21/62 , G06F21/64 , G06F21/71 , G06F21/73 , G06F21/604 , G06F21/6218 , G06F21/645 , G06F2221/2111 , G06F9/5088
摘要： Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement license management solutions for software defined silicon (SDSi) products are disclosed. Example license management solutions disclosed herein include, but are not limited to, virtual resource migration using SDSi, resource configuration management using SDSi, hardware self-configuration using SDSi, reduced footprint agents using SDSi, performing SDSi usage evaluation and corresponding license transfer responsive to detected and/or predicted failures, transferring node locked SDSi licenses, transfer of SDSi licenses without a trusted license server, community license generation, expirable SDSi licenses via a reliable clock, non-node locked licenses via blockchain, and activating hardware features with a pre-generated hardware license.

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