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11. 发明授权

US06985708B2 Linearized fractional-N synthesizer having a gated offset 有权
$Linearized fractional-N synthesizer having a gated offset$
公开(公告)号：US06985708B2
公开(公告)日：2006-01-10
申请号：US10170849
申请日：2002-06-12
申请人： Tsung-Hsien Lin , Hung-Ming Chien
发明人： Tsung-Hsien Lin , Hung-Ming Chien
IPC分类号： H04B1/06
CPC分类号： H03L7/1976 , H03L7/0891 , H04W84/042 , H04W84/18 , H04W88/02
摘要： A linearized oscillation synthesizer includes a phase and frequency detection module, charge pump circuit, low pass filter, voltage control oscillator, and a feedback module. The phase and frequency detection module is operably coupled to produce a charge-up signal, a charge-down signal, and an off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The reference oscillation is generated by a clock source such as a crystal oscillator while the divider module generates the feedback oscillation by dividing the output oscillation by a divider value. The charge pump circuit produces a positive current in response to the charge-up signal, a negative current in response to the charge-down signal and also produces a non-zero offset current. The non-zero offset current shifts the steady state operating condition, and other operating conditions, of the charge pump into a linear region of charge pump performance curve.

12. 发明授权

US06756821B2 High speed differential signaling logic gate and applications thereof 有权
标题翻译：高速差分信号逻辑门及其应用
公开(公告)号：US06756821B2
公开(公告)日：2004-06-29
申请号：US10201108
申请日：2002-07-23
申请人： Tsung-Hsien Lin
发明人： Tsung-Hsien Lin
IPC分类号： H03K1920
CPC分类号： H03K19/09432
摘要： A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, complimentary transistor, current cource, a 1st load, and a 2nd load. The 1st input transistor is operably coupled to receive a 1st input logic signal, which may be one phase of a first differential input signal. The 2nd input transistor is coupled in parallel with the 1st input transistor and is further coupled to receive a 2nd input logic signal, which may be one phase of a 2nd differential input signal. The complimentary transistor is operably coupled to the sources of the 1st and 2nd input transistors and to receive a complimentary input signal, which mimics the other phase of the 1st differential logic signal and the 2nd differential logic signal. The current source sinks a fixed current from the 1st and 2nd input transistors and the complimentary transistor. The 1st load is operably coupled to the drains of the 1st and 2nd input transistors to provide a 1st phase of a differential logic output. The 2nd load is coupled to the drain of the complimentary transistor to provide a 2nd phase of the differential logic output.
摘要翻译：高速差分信号逻辑门包括第1输入晶体管，第2输入晶体管，互补晶体管，互补晶体管，电流源，1负载和2负载。第一输入晶体管可操作地耦合以接收第一输入逻辑信号，其可以是第一差分输入信号的一相。第二输入晶体管与第一输入晶体管并联耦合，并且还被耦合以接收第二输入逻辑信号，其可以是第二差分输入信号的一相。互补晶体管可操作地耦合到第一和第二输入晶体管的源极，并且接收互补输入信号，其模拟第一差分逻辑信号的第二相，差分逻辑信号。电流源从第一和第二输入晶体管和互补晶体管吸收固定电流。第一负载可操作地耦合到第一和第二输入晶体管的漏极以提供差分逻辑输出的1相。第二负载耦合到互补晶体管的漏极，以提供差分逻辑输出的第二相。

13. 发明申请

US20120242650A1 3D GLASS, 3D IMAGE PROCESSING METHOD, COMPUTER READABLE STORAGE MEDIA CAN PERFORM THE 3D IMAGE PROCESSING METHOD 审中-公开
标题翻译： 3D玻璃，3D图像处理方法，计算机可读存储介质可执行3D图像处理方法
公开(公告)号：US20120242650A1
公开(公告)日：2012-09-27
申请号：US13070490
申请日：2011-03-24
申请人： Yu-Yeh Chen , Jia-Jio Huang , Jhen-Wei He , Heng-Shun Kuan , Tsung-Hsien Lin
发明人： Yu-Yeh Chen , Jia-Jio Huang , Jhen-Wei He , Heng-Shun Kuan , Tsung-Hsien Lin
IPC分类号： G06T15/00
CPC分类号： H04N13/373 , H04N13/122 , H04N13/341
摘要： A 3D image processing method, for processing a dynamic image region swapping between a first dynamic image gray level and a second dynamic image gray level, comprising: determining a max dynamic gray level reference value and a min dynamic gray level reference value, to generate an adjusted dynamic gray level and luminance curve; generating a dynamic table, which includes relations between the adjusted dynamic gray level and luminance curve, the first and second dynamic image gray level, according to the adjusted gray level and luminance curve; and adjusting the first and second dynamic image gray level according to the dynamic table.
摘要翻译：一种3D图像处理方法，用于处理在第一动态图像灰度级和第二动态图像灰度级之间交换的动态图像区域，包括：确定最大动态灰度级参考值和最小动态灰度级参考值，以产生调整动态灰度级和亮度曲线; 生成动态表，其中包括调整后的动态灰度级和亮度曲线之间的关系，第一和第二动态图像灰度级，根据调整的灰度级和亮度曲线; 并根据动态表调整第一和第二动态图像灰度级。

14. 发明授权

US07916064B2 Voltage-to-time converter, and voltage-to-digital converting device having the same 有权
标题翻译：电压 - 时间转换器和具有该转换器的电压 - 数字转换装置
公开(公告)号：US07916064B2
公开(公告)日：2011-03-29
申请号：US12469749
申请日：2009-05-21
申请人： Tsung-Hsien Lin , Chung-Hsing Yang , Wei-Hao Chiu
发明人： Tsung-Hsien Lin , Chung-Hsing Yang , Wei-Hao Chiu
IPC分类号： H03M1/50
CPC分类号： H03M1/50
摘要： A voltage-to-digital converting device includes a first voltage-to-time converter outputting a first delay clock having a first time delay relative to a reference clock in response to an input voltage, and a second voltage-to-time converter outputting a second delay clock having a second time delay relative to the reference clock in response to a feedback voltage. The first and second time delays correspond respectively to the input and feedback voltages. A time-to-digital converting circuit receives the first and second delay clocks from the first and second voltage-to-time converters, compares phases of the first and second delay clocks, generates the feedback voltage based on result of phase comparison made thereby, and outputs a digital signal upon detecting that the phases of the first and second delay clocks are in-phase.
摘要翻译：电压 - 数字转换装置包括第一电压 - 时间转换器，其响应于输入电压输出相对于参考时钟具有第一时间延迟的第一延迟时钟;以及第二电压 - 时间转换器，其输出第二延迟时钟响应于反馈电压具有相对于参考时钟的第二时间延迟。第一和第二时间延迟分别对应于输入和反馈电压。时间数字转换电路从第一和第二电压 - 时间转换器接收第一和第二延迟时钟，比较第一和第二延迟时钟的相位，基于由此产生的相位比较结果产生反馈电压，并且在检测到第一和第二延迟时钟的相位是同相的时，输出数字信号。

15. 发明授权

US07851800B2 Thin film transistor and organic electro-luminescent display device 有权
标题翻译：薄膜晶体管和有机电致发光显示装置
公开(公告)号：US07851800B2
公开(公告)日：2010-12-14
申请号：US12345666
申请日：2008-12-30
申请人： Tarng-Shiang Hu , Yi-Kai Wang , Jing-Yi Yan , Tsung-Hsien Lin , Jia-Chong Ho
发明人： Tarng-Shiang Hu , Yi-Kai Wang , Jing-Yi Yan , Tsung-Hsien Lin , Jia-Chong Ho
IPC分类号： H01L31/00
CPC分类号： H01L27/3262 , H01L51/524 , H01L51/5253 , H01L51/5259 , H01L2227/323 , Y10T428/24802
摘要： A TFT and an OLED device are provided. The TFT includes a substrate, a gate, a gate insulator, a source/drain layer, an isolated layer, and a channel layer. The gate is disposed on the substrate. The gate insulator is disposed on the substrate and covers the gate. The source/drain layer is disposed on the gate insulator, and exposes a portion of the gate insulator above the gate. The isolated layer is disposed on the source/drain layer and has an opening to expose a portion of the gate insulator and a portion of the source/drain layer above the gate. The channel layer is disposed in the opening of the isolated layer. Further, the channel layer is exposed by the opening and is electrically connected to the source/drain layer. On the other hand, the OLED device mainly includes a driving circuit and an organic electro-luminescent unit.
摘要翻译：提供TFT和OLED装置。 TFT包括衬底，栅极，栅极绝缘体，源极/漏极层，隔离层和沟道层。栅极设置在基板上。栅极绝缘体设置在基板上并覆盖栅极。源极/漏极层设置在栅极绝缘体上，并且将栅极绝缘体的一部分暴露在栅极上方。隔离层设置在源极/漏极层上并且具有用于暴露栅极绝缘体的一部分和栅极上方的源极/漏极层的一部分的开口。沟道层设置在隔离层的开口中。此外，沟道层由开口露出并且电连接到源极/漏极层。另一方面，OLED器件主要包括驱动电路和有机电致发光单元。

16. 发明申请

US20090298241A1 METHOD OF FABRICATING VERTICAL THIN FILM TRANSISTOR 有权
标题翻译：制造垂直薄膜晶体管的方法
公开(公告)号：US20090298241A1
公开(公告)日：2009-12-03
申请号：US12536492
申请日：2009-08-06
申请人： Yi-Kai Wang , Tsung-Hsien Lin , Tarng-Shiang Hu , Yu-Yuan Shen
发明人： Yi-Kai Wang , Tsung-Hsien Lin , Tarng-Shiang Hu , Yu-Yuan Shen
IPC分类号： H01L21/336
CPC分类号： H01L51/057 , Y10S438/944 , Y10S438/951
摘要： A method of fabricating a vertical thin film transistor (vertical TFT) is disclosed, wherein a shadow mask is used to fabricate the TFT device in vertical structure. First, a metal layer is formed, which serves as ribs and a gate layer. Next, a shadow mask is disposed on the gate layer. Afterwards, the shadow mask is used as a mask to form a source layer, an organic semiconductor layer and a drain layer. Thus, the process is simplified. Since no photolithography process is required, and therefore damage of the organic semiconductor layer is avoided and a vertical TFT with desired electrical characteristics may be obtained.
摘要翻译：公开了制造垂直薄膜晶体管（垂直TFT）的方法，其中使用荫罩来制造垂直结构的TFT器件。首先，形成用作肋和栅极层的金属层。接下来，在栅极层上设置荫罩。之后，将荫罩用作掩模以形成源极层，有机半导体层和漏极层。因此，该过程被简化。由于不需要光刻工艺，因此避免了有机半导体层的损坏，并且可以获得具有所需电特性的垂直TFT。

17. 发明申请

US20090091484A1 DELTA SIGMA MODULATOR AND METHOD FOR COMPENSATING DELTA SIGMA MODULATORS FOR LOOP DELAY 有权
标题翻译： DELTA SIGMA调制器和用于补偿DELTA SIGMA调制器的循环延迟的方法
公开(公告)号：US20090091484A1
公开(公告)日：2009-04-09
申请号：US11867034
申请日：2007-10-04
申请人： Chan-Hsiang Weng , Tsung-Hsien Lin
发明人： Chan-Hsiang Weng , Tsung-Hsien Lin
IPC分类号： H03M3/02
CPC分类号： H03M3/37 , H03M1/765 , H03M3/424 , H03M3/438
摘要： The invention provides a continuous-time delta sigma modulator. In one embodiment, the continuous-time delta sigma modulator comprises a series of integrators, a quantizer, and a loop delay compensation circuit. The integrators are coupled in series and generate an analog output signal according to an analog input signal. The quantizer quantizes the analog output signal according to a reference voltage to generate a digital output signal as the output of the continuous-time delta sigma modulator. The loop delay compensation circuit adjusts the reference voltage of the quantizer according to the digital output signal to compensate the continuous-time delta sigma modulator for a loop delay.
摘要翻译：本发明提供一种连续时间ΔΣ调制器。在一个实施例中，连续时间ΔΣ调制器包括一系列积分器，量化器和环路延迟补偿电路。积分器串联耦合，并根据模拟输入信号产生模拟输出信号。量化器根据参考电压量化模拟输出信号，以产生数字输出信号作为连续时间ΔΣ调制器的输出。环路延迟补偿电路根据数字输出信号调整量化器的参考电压，以补偿连续时间ΔΣ调制器的环路延迟。

18. 发明申请

US20090061560A1 METHOD OF FABRICATING ORGANIC ELECTRONIC DEVICE 审中-公开
标题翻译：制造有机电子器件的方法
公开(公告)号：US20090061560A1
公开(公告)日：2009-03-05
申请号：US12270863
申请日：2008-11-14
申请人： Tsung-Hsien Lin , Jia-Chong Ho , Tarng-Shiang Hu , Cheng-Chung Lee
发明人： Tsung-Hsien Lin , Jia-Chong Ho , Tarng-Shiang Hu , Cheng-Chung Lee
IPC分类号： H01L21/50
CPC分类号： H01L51/5253 , H01L51/525 , H01L2251/5338
摘要： A fabricating method of organic electronic device is provided. The method comprises: providing a flexible substrate; fabricating a plurality of organic elements on the flexible substrate; depositing a spacing material layer on the flexible substrate; patterning the spacing material layer to form a patterned spacing layer; and arranging a cover substrate on the patterned spacing layer, and sealing the edges of the flexible substrate and the cover substrate with a sealant, wherein the patterned spacing layer is used to maintain a space between the flexible substrate and the cover substrate.
摘要翻译：提供了一种有机电子器件的制造方法。该方法包括：提供柔性基底; 在柔性基板上制造多个有机元件; 在柔性基板上沉积间隔材料层; 图案化间隔材料层以形成图案化间隔层; 以及在图案化的间隔层上布置盖基板，并用密封剂密封柔性基板和盖基板的边缘，其中图案化的间隔层用于保持柔性基板和盖基板之间的空间。

19. 发明申请

US20080094558A1 Liquid crystal display having pixel regions that operate in multiple modes 有权
标题翻译：具有以多种模式操作的像素区域的液晶显示器
公开(公告)号：US20080094558A1
公开(公告)日：2008-04-24
申请号：US11974283
申请日：2007-10-12
申请人： Chun-Jui Wang , I-Lin Ho , Pei-Shan Tu , Tsung-Hsien Lin
发明人： Chun-Jui Wang , I-Lin Ho , Pei-Shan Tu , Tsung-Hsien Lin
IPC分类号： G02F1/1337 , G02F1/1343
CPC分类号： G02F1/133707 , G02F1/134309 , G02F2001/134318
摘要： A liquid crystal display device is provided that has a plurality of pixel regions where some of the pixel regions have liquid crystal molecules that operate according to both twisted nematic mode and vertical alignment mode.
摘要翻译：提供了一种液晶显示装置，其具有多个像素区域，其中一些像素区域具有根据扭曲向列模式和垂直取向模式操作的液晶分子。

20. 发明授权

US07174144B2 Calibration of a phase locked loop 有权
标题翻译：锁相环的校准
公开(公告)号：US07174144B2
公开(公告)日：2007-02-06
申请号：US10243854
申请日：2002-09-13
申请人： Tsung-Hsien Lin
发明人： Tsung-Hsien Lin
IPC分类号： H04B1/06
CPC分类号： H03L7/0891
摘要： Calibration of a phase locked loop and applications thereof within a radio frequency integrated circuit begins by determining an intersection of an up current and down current produced by a charge pump within the phase locked loop. The RFIC then determines a reference voltage corresponding to the intersection, which varies from an ideal voltage of VDD/2 based on process variations. The RFIC then offsets a control voltage to the voltage control oscillator (VCO) of the phase locked loop based on the reference voltage. Accordingly, by determining the offset of the actual intersection from the ideal intersection, the control voltage to the VCO may be adjusted thereby calibrating the phase locked loop for more linear performance.
摘要翻译：锁相环的校准及其在射频集成电路中的应用通过确定锁相环内的电荷泵产生的上升电流和下降电流的交点开始。然后，RFIC确定对应于交点的参考电压，其基于过程变化从VLS2 / 2的理想电压变化。然后，RFIC基于参考电压将控制电压偏移到锁相环的压控振荡器（VCO）。因此，通过确定实际交叉点与理想交点的偏移，可以调节到VCO的控制电压，从而校准锁相环以获得更多的线性性能。

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