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1. 发明授权

US07916064B2 Voltage-to-time converter, and voltage-to-digital converting device having the same 有权
标题翻译：电压 - 时间转换器和具有该转换器的电压 - 数字转换装置
公开(公告)号：US07916064B2
公开(公告)日：2011-03-29
申请号：US12469749
申请日：2009-05-21
申请人： Tsung-Hsien Lin , Chung-Hsing Yang , Wei-Hao Chiu
发明人： Tsung-Hsien Lin , Chung-Hsing Yang , Wei-Hao Chiu
IPC分类号： H03M1/50
CPC分类号： H03M1/50
摘要： A voltage-to-digital converting device includes a first voltage-to-time converter outputting a first delay clock having a first time delay relative to a reference clock in response to an input voltage, and a second voltage-to-time converter outputting a second delay clock having a second time delay relative to the reference clock in response to a feedback voltage. The first and second time delays correspond respectively to the input and feedback voltages. A time-to-digital converting circuit receives the first and second delay clocks from the first and second voltage-to-time converters, compares phases of the first and second delay clocks, generates the feedback voltage based on result of phase comparison made thereby, and outputs a digital signal upon detecting that the phases of the first and second delay clocks are in-phase.
摘要翻译：电压 - 数字转换装置包括第一电压 - 时间转换器，其响应于输入电压输出相对于参考时钟具有第一时间延迟的第一延迟时钟;以及第二电压 - 时间转换器，其输出第二延迟时钟响应于反馈电压具有相对于参考时钟的第二时间延迟。第一和第二时间延迟分别对应于输入和反馈电压。时间数字转换电路从第一和第二电压 - 时间转换器接收第一和第二延迟时钟，比较第一和第二延迟时钟的相位，基于由此产生的相位比较结果产生反馈电压，并且在检测到第一和第二延迟时钟的相位是同相的时，输出数字信号。

2. 发明申请

US20100182186A1 VOLTAGE-TO-TIME CONVERTER, AND VOLTAGE-TO-DIGITAL CONVERTING DEVICE HAVING THE SAME 有权
标题翻译：具有电压转换器和电压到数字转换器件
公开(公告)号：US20100182186A1
公开(公告)日：2010-07-22
申请号：US12469749
申请日：2009-05-21
申请人： Tsung-Hsien Lin , Chung-Hsing Yang , Wei-Hao Chiu
发明人： Tsung-Hsien Lin , Chung-Hsing Yang , Wei-Hao Chiu
IPC分类号： H03M1/50
CPC分类号： H03M1/50
摘要： A voltage-to-digital converting device includes a first voltage-to-time converter outputting a first delay clock having a first time delay relative to a reference clock in response to an input voltage, and a second voltage-to-time converter outputting a second delay clock having a second time delay relative to the reference clock in response to a feedback voltage. The first and second time delays correspond respectively to the input and feedback voltages. A time-to-digital converting circuit receives the first and second delay clocks from the first and second voltage-to-time converters, compares phases of the first and second delay clocks, generates the feedback voltage based on result of phase comparison made thereby, and outputs a digital signal upon detecting that the phases of the first and second delay clocks are in-phase.
摘要翻译：电压 - 数字转换装置包括第一电压 - 时间转换器，其响应于输入电压输出相对于参考时钟具有第一时间延迟的第一延迟时钟;以及第二电压 - 时间转换器，其输出第二延迟时钟响应于反馈电压具有相对于参考时钟的第二时间延迟。第一和第二时间延迟分别对应于输入和反馈电压。时间数字转换电路从第一和第二电压 - 时间转换器接收第一和第二延迟时钟，比较第一和第二延迟时钟的相位，基于由此产生的相位比较结果产生反馈电压，并且在检测到第一和第二延迟时钟的相位是同相的时，输出数字信号。

3. 发明授权

US08437441B2 Phase locked loop capable of fast locking 有权
标题翻译：锁相环能够快速锁定
公开(公告)号：US08437441B2
公开(公告)日：2013-05-07
申请号：US12506023
申请日：2009-07-20
申请人： Tsung-Hsien Lin , Wei-Hao Chiu , Yu-Hsiang Huang
发明人： Tsung-Hsien Lin , Wei-Hao Chiu , Yu-Hsiang Huang
IPC分类号： H03D3/24
CPC分类号： H03L7/085 , H03L7/081 , H03L7/0893 , H03L7/1075 , H03L2207/06
摘要： A phase locked loop includes a voltage controlled oscillator operable to generate an output signal corresponding to a reference signal in response to a control voltage signal outputted by a filter in response to a current signal, and a variable frequency divider operable to perform frequency division on the output signal using a variable divisor so as to generate a divided feedback signal. A charge pump outputs the current signal in response to a phase detecting output from a phase/frequency detector indicating phases of the divided feedback signal and the reference signal. A phase error comparator outputs, in accordance with the phase detecting output, a digital output indicating whether the divided feedback signal lags or leads the reference signal and further indicating a phase difference between the divided feedback signal and the reference signal. The variable frequency divider determines a value of the variable divisor in accordance with the digital output to reduce the phase difference between the divided feedback signal and the reference signal.
摘要翻译：锁相环包括压控振荡器，其可操作以响应于由电流信号响应由滤波器输出的控制电压信号而产生对应于参考信号的输出信号;以及可变分频器，用于对输出信号，以产生分频的反馈信号。响应于来自相位/频率检测器的相位检测输出，电荷泵输出指示分频反馈信号和参考信号的相位的电流信号。相位误差比较器根据相位检测输出输出指示分频反馈信号是否滞后或引导参考信号的数字输出，并进一步指示分频反馈信号与参考信号之间的相位差。可变分频器根据数字输出确定可变因数的值，以减小分频反馈信号与参考信号之间的相位差。

4. 发明申请

US20100183109A1 PHASE LOCKED LOOP CAPABLE OF FAST LOCKING 有权
标题翻译：快速锁定的相位锁定环路
公开(公告)号：US20100183109A1
公开(公告)日：2010-07-22
申请号：US12506023
申请日：2009-07-20
申请人： Tsung-Hsien Lin , Wei-Hao Chiu , Yu-Hsiang Huang
发明人： Tsung-Hsien Lin , Wei-Hao Chiu , Yu-Hsiang Huang
IPC分类号： H03D3/24
CPC分类号： H03L7/085 , H03L7/081 , H03L7/0893 , H03L7/1075 , H03L2207/06
摘要： A phase locked loop includes a voltage controlled oscillator operable to generate an output signal corresponding to a reference signal in response to a control voltage signal outputted by a filter in response to a current signal, and a variable frequency divider operable to perform frequency division on the output signal using a variable divisor so as to generate a divided feedback signal. A charge pump outputs the current signal in response to a phase detecting output from a phase/frequency detector indicating phases of the divided feedback signal and the reference signal. A phase error comparator outputs, in accordance with the phase detecting output, a digital output indicating whether the divided feedback signal lags or leads the reference signal and further indicating a phase difference between the divided feedback signal and the reference signal. The variable frequency divider determines a value of the variable divisor in accordance with the digital output to reduce the phase difference between the divided feedback signal and the reference signal .
摘要翻译：锁相环包括压控振荡器，其可操作以响应于由电流信号响应由滤波器输出的控制电压信号而产生对应于参考信号的输出信号;以及可变分频器，用于对输出信号，以产生分频的反馈信号。响应于来自相位/频率检测器的相位检测输出，电荷泵输出指示分频反馈信号和参考信号的相位的电流信号。相位误差比较器根据相位检测输出输出指示分频反馈信号是否滞后或引导参考信号的数字输出，并进一步指示分频反馈信号与参考信号之间的相位差。可变分频器根据数字输出确定可变因数的值，以减小分频反馈信号与参考信号之间的相位差。

5. 发明申请

US20120055796A1 METHOD OF FABRICATING ELECTRODE STRUCTURES ON SUBSTRATE 有权
标题翻译：在基板上制作电极结构的方法
公开(公告)号：US20120055796A1
公开(公告)日：2012-03-08
申请号：US13085452
申请日：2011-04-12
申请人： Kun-Mu Lee , Sz-Ping Fu , Wei-Hao Chiu , Chuan-Ya Hung
发明人： Kun-Mu Lee , Sz-Ping Fu , Wei-Hao Chiu , Chuan-Ya Hung
IPC分类号： C25D15/00 , B82Y99/00
CPC分类号： C25D5/02 , B82Y30/00 , C25D5/10 , C25D15/00
摘要： Methods for fabricating electrode structures on a substrate are presented. The fabrication method includes providing a substrate with a patterned metal layer thereon, defining an electrode area. A passivation glue is formed on the patterned metal layer. An electrode layer is formed in the electrode area. A filling process is performed to deposit nano metal oxides on the electrode layer to extensively fill the entire electrode area.
摘要翻译：介绍了在基板上制作电极结构的方法。制造方法包括在其上提供其上具有图案化金属层的基底，限定电极区域。在图案化金属层上形成钝化胶。在电极区域中形成电极层。进行填充处理以在电极层上沉积纳米金属氧化物，以广泛填充整个电极区域。

6. 发明授权

US08470150B2 Method of fabricating electrode structures on substrate 有权
标题翻译：在基片上制作电极结构的方法
公开(公告)号：US08470150B2
公开(公告)日：2013-06-25
申请号：US13085452
申请日：2011-04-12
申请人： Kun-Mu Lee , Sz-Ping Fu , Wei-Hao Chiu , Chuan-Ya Hung
发明人： Kun-Mu Lee , Sz-Ping Fu , Wei-Hao Chiu , Chuan-Ya Hung
IPC分类号： C25D13/02
CPC分类号： C25D5/02 , B82Y30/00 , C25D5/10 , C25D15/00
摘要： Methods for fabricating electrode structures on a substrate are presented. The fabrication method includes providing a substrate with a patterned metal layer thereon, defining an electrode area. A passivation glue is formed on the patterned metal layer. An electrode layer is formed in the electrode area. A filling process is performed to deposit nano metal oxides on the electrode layer to extensively fill the entire electrode area.
摘要翻译：介绍了在基板上制作电极结构的方法。制造方法包括在其上提供其上具有图案化金属层的基底，限定电极区域。在图案化金属层上形成钝化胶。在电极区域中形成电极层。进行填充处理以在电极层上沉积纳米金属氧化物，以广泛填充整个电极区域。

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