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11. 发明授权

US07366822B2 Semiconductor memory device capable of reading and writing data at the same time 有权
标题翻译：能够同时读取和写入数据的半导体存储器件
公开(公告)号：US07366822B2
公开(公告)日：2008-04-29
申请号：US10840268
申请日：2004-05-07
申请人： Jin-Seok Kwak , Young-Hyun Jun , Seong-Jin Jang , Sang-Bo Lee , Min-Sang Park , Chul-Soo Kim
发明人： Jin-Seok Kwak , Young-Hyun Jun , Seong-Jin Jang , Sang-Bo Lee , Min-Sang Park , Chul-Soo Kim
IPC分类号： G06F12/00 , G11C8/00
CPC分类号： G11C7/1066 , G11C7/1072 , G11C11/4082 , G11C11/4087
摘要： A semiconductor memory device includes a plurality of banks. A data path may be divided into a read data path and a write data path, therefore, parallel processing of write and read commands are possible. The semiconductor memory device may include an address bank buffer, address buffer, column predecoder and/or a decoder. The semiconductor memory device may begin execution of a write command in a bank in one clock cycle and begin execution of a read command in the following clock cycle, therefore, bus efficiency is increased and/or write-to-read turn around time is reduced.
摘要翻译：半导体存储器件包括多个存储体。数据路径可以被划分为读取数据路径和写入数据路径，因此并行处理写入和读取命令是可能的。半导体存储器件可以包括地址库缓冲器，地址缓冲器，列预解码器和/或解码器。半导体存储器件可以在一个时钟周期内开始执行存储体中的写入命令，并且在随后的时钟周期开始执行读取命令，因此总线效率增加和/或写入读取时间减少。

12. 发明申请

US20070185670A1 Methods of Measuring Frequencies Including Charging Electrical Circuits 审中-公开
标题翻译：测量包括充电电路在内的频率的方法
公开(公告)号：US20070185670A1
公开(公告)日：2007-08-09
申请号：US11733220
申请日：2007-04-10
申请人： Hyun-Jin Kim , Sang-Bo Lee
发明人： Hyun-Jin Kim , Sang-Bo Lee
IPC分类号： G01R23/00
CPC分类号： G11C7/22 , G11C7/16 , G11C7/222
摘要： A method of measuring a frequency of an input clock signal may include generating an output pulse responsive to an edge of the input clock signal, and charging an electrical circuit responsive to the output pulse. An analog output signal may be generated responsive to the charged electrical circuit, and the analog output signal may be converted into a digital value representing a frequency of the input clock signal. Related frequency measuring circuits and memory devices are also discussed.
摘要翻译：测量输入时钟信号的频率的方法可以包括响应于输入时钟信号的边缘产生输出脉冲，以及响应于输出脉冲对电路充电。可以响应于充电的电路产生模拟输出信号，并且模拟输出信号可以被转换成表示输入时钟信号的频率的数字值。还讨论了相关的频率测量电路和存储器件。

13. 发明申请

US20060028888A1 Semiconductor memory device having local sense amplifier with on/off control 有权
标题翻译：具有开/关控制的本地读出放大器的半导体存储器件
公开(公告)号：US20060028888A1
公开(公告)日：2006-02-09
申请号：US11188184
申请日：2005-07-20
申请人： Sang-Woong Shin , Chul-Soo Kim , Young-Hyun Jun , Sang-Bo Lee
发明人： Sang-Woong Shin , Chul-Soo Kim , Young-Hyun Jun , Sang-Bo Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/06 , G11C11/4091 , G11C2207/005 , G11C2207/065
摘要： A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.
摘要翻译：半导体存储器件包括多个存储单元阵列块，位线读出放大器，可被控制为导通或截止的本地读出放大器，数据读出放大器和控制器。控制器响应于第一和第二信号激活预定持续时间的局部感测控制信号。第一信号是激活位线读出放大器的位线检测使能信号，并且在位线检测使能信号被激活之后局部读出放大器被激活预定的持续时间。第二信号与连接一对位线和一对本地输入/输出线的列选择线信号同相激活或去激活。因此，可以根据操作条件接通或关闭本地读出放大器，由此增加tRCD参数并减少电流消耗。可以通过组合本地读出放大器与在读取操作期间不需要预充电和均衡的电流型数据读出放大器来提高半导体存储器件的工作速度。

14. 发明申请

US20070195625A1 Local sense amplifier in memory device 失效
标题翻译：存储器中的本地读出放大器
公开(公告)号：US20070195625A1
公开(公告)日：2007-08-23
申请号：US11789395
申请日：2007-04-24
申请人： Sang-Bo Lee
发明人： Sang-Bo Lee
IPC分类号： G11C7/00 , G11C5/06
CPC分类号： G11C7/18 , G11C7/062
摘要： A memory device includes a decoder that sets an operational control signal and a column select line signal at a first logical level simultaneously. In addition, a local sense amplifier has at least one switching device that is turned on by the operational control signal that is at the first logical level to couple at least one local I/O line to at least one global I/O line. Furthermore, signal lines, that are disposed to be parallel, transmit the operational control signal and the column select line signal from the decoder.
摘要翻译：存储器件包括一个解码器，它同时设置第一逻辑电平的操作控制信号和列选择线信号。另外，本地读出放大器具有至少一个开关装置，该开关装置由处于第一逻辑电平的操作控制信号导通，以将至少一个本地I / O线耦合到至少一个全局I / O线。此外，被设置为并联的信号线从解码器发送操作控制信号和列选择线信号。

15. 发明申请

US20060250162A1 SIGNAL AMPLIFICATION CIRCUIT FOR HIGH-SPEED OPERATION AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME 审中-公开
标题翻译：用于高速操作的信号放大电路和具有该功能的半导体存储器件
公开(公告)号：US20060250162A1
公开(公告)日：2006-11-09
申请号：US11379200
申请日：2006-04-18
申请人： Du-Yeul Kim , Jun-Hyung Kim , Tai-Young Ko , Sang-Bo Lee
发明人： Du-Yeul Kim , Jun-Hyung Kim , Tai-Young Ko , Sang-Bo Lee
IPC分类号： H03F3/45
CPC分类号： G11C7/1072 , G11C7/1051 , G11C7/1069
摘要： A signal amplification circuit for a semiconductor memory device includes a current sense amplifier configured to receive a first signal pair and generate a second signal pair on a first pair of lines, an equalizer configured to equalize the first pair of lines, and a latch amplifier configured to generate a latch data output on a second pair of lines in response to the second signal pair.
摘要翻译：一种用于半导体存储器件的信号放大电路包括：电流检测放大器，被配置为接收第一信号对并在第一对线路上产生第二信号对，配置成对第一对线路进行均衡的均衡器和配置成以响应于第二信号对在第二对线路上产生锁存数据输出。

16. 发明授权

US07038963B2 Current sense amplifier circuits having a bias voltage node for adjusting input resistance 失效
标题翻译：电流检测放大器电路具有用于调节输入电阻的偏置电压节点
公开(公告)号：US07038963B2
公开(公告)日：2006-05-02
申请号：US11068353
申请日：2005-02-28
申请人： Sang-Bo Lee
发明人： Sang-Bo Lee
IPC分类号： G11C7/02
CPC分类号： G11C11/4091 , G11C7/04
摘要： A current sense amplifier includes first and second P type MOS transistors having source nodes connected to first and second sensing inputs, respectively, and gate and drain nodes being cross-coupled to each other. First and second N type MOS transistors have drain nodes connected to first and second sensing outputs, respectively, the first and second sensing outputs corresponding to the drain nodes of the first and second P type MOS transistors, respectively, the first and second N type MOS transistors having respective gate nodes connected to a power supply voltage. Third and fourth N type MOS transistors have drain nodes connected to the first and second sensing outputs, respectively, and gate nodes connected to a bias voltage node so that respective current paths are established from the first and second sensing outputs to a common reference node.
摘要翻译：电流检测放大器包括分别连接到第一和第二感测输入的源节点的第一和第二P型MOS晶体管，并且栅极和漏极节点彼此交叉耦合。第一和第二N型MOS晶体管具有分别连接到第一和第二感测输出的漏极节点，分别对应于第一和第二P型MOS晶体管的漏极节点的第一和第二感测输出，第一和第二N型MOS 具有连接到电源电压的各个栅极节点的晶体管。第三和第四N型MOS晶体管分别具有连接到第一和第二感测输出的漏极节点，以及连接到偏置电压节点的栅极节点，使得各自的电流路径从第一和第二感测输出建立到公共参考节点。

17. 发明授权

US5638333A Bit line sensing circuit and method of a semiconductor memory device 失效
标题翻译：半导体存储器件的位线检测电路和方法
公开(公告)号：US5638333A
公开(公告)日：1997-06-10
申请号：US487324
申请日：1995-06-07
申请人： Sang-Bo Lee
发明人： Sang-Bo Lee
IPC分类号： G11C11/419 , G11C7/06 , G11C11/407 , G11C11/409 , G11C11/4091 , G11C7/00
CPC分类号： G11C11/4091 , G11C7/065
摘要： A bit line sensing circuit of a semiconductor memory device having NMOS and PMOS sense amps connected to a bit line includes a variable delay path for variably controlling an interval of the operating time between the NMOS and PMOS sense amps in response to a power voltage sensing signal generated by sensing a power voltage level.
摘要翻译：具有连接到位线的NMOS和PMOS检测放大器的半导体存储器件的位线检测电路包括可变延迟路径，用于响应于电源电压感测信号可变地控制NMOS和PMOS检测放大器之间的工作时间的间隔通过感测电源电压电平产生。

18. 发明授权

US09715740B2 Methods of and apparatuses for recognizing motion of objects, and associated systems 有权
公开(公告)号：US09715740B2
公开(公告)日：2017-07-25
申请号：US14064639
申请日：2013-10-28
申请人： Young-Gu Jin , Jung-Seop Kim , Dong-Wook Kwon , Kyung-Il Kim , Min Ho Kim , Gi-Sang Lee , Sang-Bo Lee , Jin-Kyung Lee , Jin-Wuk Choi
发明人： Young-Gu Jin , Jung-Seop Kim , Dong-Wook Kwon , Kyung-Il Kim , Min Ho Kim , Gi-Sang Lee , Sang-Bo Lee , Jin-Kyung Lee , Jin-Wuk Choi
IPC分类号： G06T7/254
CPC分类号： G06T7/254 , G06T2207/10016 , G06T2207/10024 , G06T2207/10028 , G06T2207/30232 , G06T2207/30241
摘要： A method of recognizing motion of an object may include periodically obtaining depth data of a first resolution and two-dimensional data of a second resolution with respect to a scene using an image capturing device, wherein the second resolution is higher than the first resolution; determining a motion tracking region by recognizing a target object in the scene based on the depth data, such that the motion tracking region corresponds to a portion of a frame and the portion includes the target object; periodically obtaining tracking region data of the second resolution corresponding to the motion tracking region; and/or analyzing the motion of the target object based on the tracking region data.

19. 发明申请

US20150221361A1 Semiconductor Memory Devices Including Redundancy Memory Cells 有权
标题翻译：包括冗余存储器单元的半导体存储器件
公开(公告)号：US20150221361A1
公开(公告)日：2015-08-06
申请号：US14503691
申请日：2014-10-01
申请人： Yun-Young Lee , Kyo-Min Sohn , Sang-Joon Hwang , Sung-Min Seo , Sang-Bo Lee , Nak-Won Heo
发明人： Yun-Young Lee , Kyo-Min Sohn , Sang-Joon Hwang , Sung-Min Seo , Sang-Bo Lee , Nak-Won Heo
IPC分类号： G11C11/406 , G11C11/408 , G11C17/16
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C17/16 , G11C29/44 , G11C29/783 , G11C29/785 , G11C2029/4402
摘要： A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.
摘要翻译：半导体存储器件包括存储单元阵列，修复控制电路和刷新控制电路。存储单元阵列包括多个存储单元和多个冗余存储单元。修复控制电路在修复模式期间接收修复命令并对多个存储单元中的第一有缺陷存储单元执行修复操作。半导体存储器件可以响应于修复命令在修复模式下操作。刷新控制电路在修复模式期间对多个存储单元中的无缺陷存储单元执行刷新操作。

20. 发明申请

US20110069568A1 SEMICONDUCTOR MEMORY DEVICE HAVING LOCAL SENSE AMPLIFIER WITH ON/OFF CONTROL 审中-公开
标题翻译：具有开/关控制的本地信号放大器的半导体存储器件
公开(公告)号：US20110069568A1
公开(公告)日：2011-03-24
申请号：US12952328
申请日：2010-11-23
申请人： Sang-Woong Shin , Chul-Soo Kim , Young-Hyun Jun , Sang-Bo Lee
发明人： Sang-Woong Shin , Chul-Soo Kim , Young-Hyun Jun , Sang-Bo Lee
IPC分类号： G11C7/08 , G11C7/12 , G11C7/22
CPC分类号： G11C7/06 , G11C11/4091 , G11C2207/005 , G11C2207/065
摘要： A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current. The operating speed of the semiconductor memory device can be improved by combining the local sense amplifier with a current type data sense amplifier that does not require precharging and equalization during a read operation.
摘要翻译：半导体存储器件包括多个存储单元阵列块，位线读出放大器，可被控制为导通或截止的本地读出放大器，数据读出放大器和控制器。控制器响应于第一和第二信号激活预定持续时间的局部感测控制信号。第一信号是激活位线读出放大器的位线检测使能信号，并且在位线检测使能信号被激活之后局部读出放大器被激活预定的持续时间。第二信号与连接一对位线和一对本地输入/输出线的列选择线信号同相激活或去激活。因此，可以根据操作条件接通或关闭本地读出放大器，由此增加tRCD参数并减少电流消耗。可以通过组合本地读出放大器与在读取操作期间不需要预充电和均衡的电流型数据读出放大器来提高半导体存储器件的工作速度。

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