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11. 发明授权

US07539055B2 Non-volatile semiconductor memory and method for controlling a non-volatile semiconductor memory 失效
标题翻译：非挥发性半导体存储器和用于控制非易失性半导体存储器的方法
公开(公告)号：US07539055B2
公开(公告)日：2009-05-26
申请号：US11763204
申请日：2007-06-14
申请人： Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Fumitaka Arai , Riichiro Shirota
发明人： Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Fumitaka Arai , Riichiro Shirota
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： A non-volatile semiconductor memory includes a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.
摘要翻译：非易失性半导体存储器包括多个存储单元晶体管，多个存储单元晶体管中的每一个包括：具有第一导电类型并与支撑衬底上的埋置绝缘层接触的源极区; 具有第一导电类型并与埋入绝缘层接触的漏极区; 以及具有第一导电类型并且设置在源区和漏区之间以与掩埋绝缘层接触的沟道区，其中沟道区的厚度大于1nm且不大于通过将7 nm到存储单元晶体管的栅极长度的一半值。

12. 发明授权

US07528447B2 Non-volatile semiconductor memory and method for controlling a non-volatile semiconductor memory 失效
标题翻译：非挥发性半导体存储器和用于控制非易失性半导体存储器的方法
公开(公告)号：US07528447B2
公开(公告)日：2009-05-05
申请号：US11396507
申请日：2006-04-05
申请人： Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Fumitaka Arai , Riichiro Shirota
发明人： Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Fumitaka Arai , Riichiro Shirota
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： A non-volatile semiconductor memory including a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.
摘要翻译：一种包括多个存储单元晶体管的非易失性半导体存储器，所述多个存储单元晶体管中的每一个包括：具有第一导电类型并与支撑衬底上的埋置绝缘层接触的源极区; 具有第一导电类型并与埋入绝缘层接触的漏极区; 以及具有第一导电类型并且设置在源区和漏区之间以与掩埋绝缘层接触的沟道区，其中沟道区的厚度大于1nm且不大于通过将7 nm到存储单元晶体管的栅极长度的一半值。

13. 发明申请

US20070290253A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20070290253A1
公开(公告)日：2007-12-20
申请号：US11765881
申请日：2007-06-20
申请人： Masaru KITO , Nobutoshi Aoki , Masaru Kidoh , Ryota Katsumata , Masaki Kondo , Naoki Kusunoki , Toshiyuki Enda , Sanae Ito , Hiroyoshi Tanimoto , Hideaki Aochi , Akihiro Nitayama , Riichiro Shirota
发明人： Masaru KITO , Nobutoshi Aoki , Masaru Kidoh , Ryota Katsumata , Masaki Kondo , Naoki Kusunoki , Toshiyuki Enda , Sanae Ito , Hiroyoshi Tanimoto , Hideaki Aochi , Akihiro Nitayama , Riichiro Shirota
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/42336
摘要： A nonvolatile semiconductor memory device includes: a semiconductor region; device isolation regions placed in the semiconductor region and extending in a column direction; a semiconductor layer placed on the semiconductor region and between the device isolation regions, and having a convex shape in cross section along a row direction; source/drain regions placed in the semiconductor layer and spaced from each other; a gate insulating film placed on the semiconductor layer between the source/drain regions; a floating gate electrode layer placed on the gate insulating film; an intergate insulating film placed on the floating gate electrode layer and upper surfaces of the device isolation regions; and a control gate electrode layer placed on the intergate insulating film and extending in the row direction.
摘要翻译：非易失性半导体存储器件包括：半导体区域; 器件隔离区域放置在半导体区域中并沿列方向延伸; 放置在半导体区域和器件隔离区之间的半导体层，沿着行方向具有凸形的横截面; 源极/漏极区域放置在半导体层中并彼此间隔开; 位于源极/漏极区之间的半导体层上的栅极绝缘膜; 放置在栅极绝缘膜上的浮栅电极层; 布置在浮栅电极层和器件隔离区的上表面上的隔间绝缘膜; 以及控制栅极电极层，其设置在所述隔间绝缘膜上并沿行方向延伸。

14. 发明申请

US20070237002A1 NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR CONTROLLING A NON-VOLATILE SEMICONDUCTOR MEMORY 失效
标题翻译：非挥发性半导体存储器和控制非易失性半导体存储器的方法
公开(公告)号：US20070237002A1
公开(公告)日：2007-10-11
申请号：US11763204
申请日：2007-06-14
申请人： Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Fumitaka Arai , Riichiro Shirota
发明人： Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Fumitaka Arai , Riichiro Shirota
IPC分类号： G11C16/24
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： A non-volatile semiconductor memory includes a plurality of memory cell transistors, each of the plurality of memory cell transistors includes: a source region having a first conductivity type and in contact with a buried insulating layer on a supporting substrate; a drain region having the first conductivity type and in contact with the buried insulating layer; and a channel region having the first conductivity type and provided between the source region and the drain region so as to contact the buried insulating layer, wherein a thickness of the channel region is more than one nm and not more than a value obtained by adding seven nm to a half value of a gate length of the memory cell transistor.
摘要翻译：非易失性半导体存储器包括多个存储单元晶体管，多个存储单元晶体管中的每一个包括：具有第一导电类型并与支撑衬底上的埋置绝缘层接触的源极区; 具有第一导电类型并与埋入绝缘层接触的漏极区; 以及具有第一导电类型并且设置在源区和漏区之间以与掩埋绝缘层接触的沟道区，其中沟道区的厚度大于1nm且不大于通过将7 nm到存储单元晶体管的栅极长度的一半值。

15. 发明申请

US20070138536A1 METHOD OF FABRICATING A SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US20070138536A1
公开(公告)日：2007-06-21
申请号：US11609614
申请日：2006-12-12
申请人： Fumitaka ARAI , Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Riichiro Shirota , Hiroshi Watanabe , Takamitsu Ishihara
发明人： Fumitaka ARAI , Toshiyuki Enda , Hiroyoshi Tanimoto , Naoki Kusunoki , Nobutoshi Aoki , Riichiro Shirota , Hiroshi Watanabe , Takamitsu Ishihara
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A NAND cell unit is formed with an advanced gate forming process on a semiconductor layer of a first conductivity type, which is formed on a semiconductor substrate of the first conductivity type with an insulating film interposed therebetween. First impurity-doped layers of a second conductivity type are formed on the semiconductor layer, which serve as channel regions of the select gate transistors Bit line contact- and source line contact-use second impurity-doped layers of the first conductivity type are formed at bit line and source line contact portions, sidewalls of which are covered with an insulating film.
摘要翻译： NAND单元单元在第一导电类型的半导体层上形成有先进的栅极形成工艺，该第一导电类型的半导体层形成在第一导电类型的半导体衬底上，绝缘膜插入其间。第一导电类型的第一杂质掺杂层形成在用作选择栅晶体管的沟道区的半导体层上。第一导电类型的位线接触和源极接触用第二杂质掺杂层形成在位线和源极线接触部分，其侧壁被绝缘膜覆盖。

16. 发明授权

US5889687A Simulator, simulation and fabrication methods of semiconductor device and storage medium storing program for executing the simulation method 失效
公开(公告)号：US5889687A
公开(公告)日：1999-03-30
申请号：US61867
申请日：1998-04-17
申请人： Toshiyuki Enda
发明人： Toshiyuki Enda
IPC分类号： H01L29/00 , G06F17/00 , G06F17/50 , H01L21/00 , H01L21/02
CPC分类号： G06F17/5036
摘要： The present invention provides a device simulation method comprising at least the steps of: inputting a geometry of a semiconductor device, a donor and an acceptor impurity concentrations at each point inside the semiconductor device and also terminal voltages of the semiconductor device (step S101); setting initial values by obtaining electron concentrations n, and n.sub.J and also hole concentrations p.sub.I and p.sub.J with respect to given points I and J respectively inside the semiconductor device and also a potential at each point (step S102); obtaining a voltage difference .PSI..sub.dd across a prescribed segment dd along a segment IJ connecting the points I and J (step S103); calculating an electron current density J.sub.eIJ of the segment IJ by an equation J.sub.eLJ =C.sub.eI .multidot.A(.PHI..sub.edd)-C.sub.eJ .multidot.A(-.PHI..sub.edd) using a constant C.sub.eI dependent on the electron concentration n.sub.J, a constant C.sub.eJ dependent on the electron concentration n.sub.J, and a voltage difference (.PHI..sub.edd =.PSI..sub.dd /NV.sub.e) across the segment dd normalized by an electron's thermal voltage (NV.sub.e =k.multidot.T.sub.e /(-q)) (step S104); calculating a hole current density J.sub.hIJ of the segment IJ by an equation J.sub.hIJ =C.sub.hI .multidot.A(.PHI..sub.hdd)-C.sub.hJ .multidot.A(-.PHI..sub.hdd) using a constant C.sub.hI dependent on the hole concentration p.sub.I, a constant C.sub.hJ dependent on the hole concentration p.sub.J, and a voltage difference ((.PHI..sub.hdd =.PSI..sub.dd /NV.sub.h) across the segment dd normalized by a hole's thermal voltage (NV.sub.h =k.multidot.T.sub.h /q) (step S105); and outputting a terminal current, where A(.PHI.)=1/(exp(.PHI.)+1). The present invention provides also a device simulator that can perform this device simulation method for fabricating semiconductor devices, and a storage medium storing the program to perform this device simulation method. The present invention further provides a device fabrication method employing the device simulation method.

17. 发明申请

US20110303958A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20110303958A1
公开(公告)日：2011-12-15
申请号：US13156702
申请日：2011-06-09
申请人： Kouji MATSUO , Toshiyuki Enda , Nobutoshi Aoki , Toshihiko Iinuma
发明人： Kouji MATSUO , Toshiyuki Enda , Nobutoshi Aoki , Toshihiko Iinuma
IPC分类号： H01L29/792 , H03K19/08 , H01L21/336
CPC分类号： H01L29/7926 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C2213/18 , G11C2213/71 , G11C2213/75 , H01L27/11565 , H01L27/11568 , H01L27/24
摘要： According to one embodiment, a nonvolatile semiconductor memory includes control gates provided in an array form, the control gates passing through the first semiconductor layer, data recording layers between the first semiconductor layer and the control gates, two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer, two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer, select gate lines extending in the first direction on the first semiconductor layer, and word lines extending in the second direction on the select gate lines. The select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction. Each of the word lines is commonly connected to the control gates arranged in the second direction.
摘要翻译：根据一个实施例，非易失性半导体存储器包括以阵列形式提供的控制栅极，通过第一半导体层的控制栅极，第一半导体层和控制栅极之间的数据记录层，两个第一导电型扩散层在第一半导体层的第一方向上结束，在第一半导体层的第二方向上的两端处的两个第二导电型扩散层，在第一半导体层上沿第一方向延伸的选择栅极线，选择栅极线上的第二个方向。选择栅极线用作连接在控制栅极和沿第一方向布置的字线之间的选择晶体管共享的选择栅极。每条字线通常连接到沿第二方向布置的控制门。

18. 发明授权

US07956408B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07956408B2
公开(公告)日：2011-06-07
申请号：US12021003
申请日：2008-01-28
申请人： Toshiyuki Enda , Hirosyoshi Tanimoto , Takashi Izumida
发明人： Toshiyuki Enda , Hirosyoshi Tanimoto , Takashi Izumida
IPC分类号： H01L27/115
CPC分类号： H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device relating to one embodiment of this invention includes a substrate, a plurality of memory strings formed on said substrate, said memory string having a first select gate transistor, a plurality of memory cells and a second select gate transistor, said first select gate transistor having a first pillar semiconductor, a first gate insulation layer formed around said first pillar semiconductor and a first gate electrode being formed around said first gate insulation layer; said memory cell having a second pillar semiconductor, a first insulation layer formed around said second pillar semiconductor, a storage layer formed around said first insulation layer, a second insulation layer formed around said storage layer and first to nth electrodes (n is a natural number 2 or more) being formed around said second insulation layer, said first to nth electrodes being spread in two dimensions respectively, said second select gate transistor having a third pillar semiconductor, a second gate insulation layer formed around said third pillar semiconductor and a second gate electrode being formed around said second gate insulation layer, and a channel region of at least either said first select gate transistor or said second select gate transistor formed by an opposite conductive type semiconductor to a source region and a drain region.
摘要翻译：关于本发明的一个实施例的非易失性半导体存储器件包括衬底，形成在所述衬底上的多个存储器串，所述存储器串具有第一选择栅晶体管，多个存储单元和第二选择栅晶体管，所述第一选择具有第一柱状半导体的栅极晶体管，形成在所述第一柱状半导体周围的第一栅极绝缘层和围绕所述第一栅极绝缘层形成的第一栅极电极; 所述存储单元具有第二柱状半导体，围绕所述第二柱状半导体形成的第一绝缘层，围绕所述第一绝缘层形成的存储层，形成在所述存储层和第一至第n电极周围的第二绝缘层（n为自然数） 2个或更多个），所述第一至第n电极分别以两维扩展，所述第二选择栅晶体管具有第三柱半导体，围绕所述第三柱半导体形成的第二栅绝缘层和第二栅极形成在所述第二栅极绝缘层周围的电极，以及至少所述第一选择栅极晶体管或所述第二选择栅极晶体管的沟道区域，所述沟道区域由相对的导电型半导体形成为源极区域和漏极区域。

19. 发明申请

US20080253181A1 METHOD FOR PROGRAMMING A SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：用于编程半导体存储器件的方法
公开(公告)号：US20080253181A1
公开(公告)日：2008-10-16
申请号：US12061105
申请日：2008-04-02
申请人： Toshiaki Edahiro , Takuya Futatsuyama , Toshiyuki Enda
发明人： Toshiaki Edahiro , Takuya Futatsuyama , Toshiyuki Enda
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3418 , G11C16/3427
摘要： A method for programming a semiconductor memory device including such a program sequence as to program target threshold levels constituting multi-level data into multiple memory cells, which are simultaneously selected, wherein the program sequence is controlled to finish programming the multiple memory cells in order of height of the target threshold levels.
摘要翻译：一种编程半导体存储器件的方法，该半导体存储器件包括这样的程序序列，将构成多级数据的程序目标阈值水平同时选择为多个存储器单元，其中控制该程序序列以完成对多个存储器单元的编程，目标阈值水平的高度。

20. 发明授权

US08633535B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08633535B2
公开(公告)日：2014-01-21
申请号：US13156702
申请日：2011-06-09
申请人： Kouji Matsuo , Toshiyuki Enda , Nobutoshi Aoki , Toshihiko Iinuma
发明人： Kouji Matsuo , Toshiyuki Enda , Nobutoshi Aoki , Toshihiko Iinuma
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C2213/18 , G11C2213/71 , G11C2213/75 , H01L27/11565 , H01L27/11568 , H01L27/24
摘要： According to one embodiment, a nonvolatile semiconductor memory includes control gates provided in an array form, the control gates passing through the first semiconductor layer, data recording layers between the first semiconductor layer and the control gates, two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer, two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer, select gate lines extending in the first direction on the first semiconductor layer, and word lines extending in the second direction on the select gate lines. The select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction. Each of the word lines is commonly connected to the control gates arranged in the second direction.
摘要翻译：根据一个实施例，非易失性半导体存储器包括以阵列形式提供的控制栅极，通过第一半导体层的控制栅极，第一半导体层和控制栅极之间的数据记录层，两个第一导电型扩散层在第一半导体层的第一方向上结束，在第一半导体层的第二方向上的两端处的两个第二导电型扩散层，在第一半导体层上沿第一方向延伸的选择栅极线，选择栅极线上的第二个方向。选择栅极线用作连接在控制栅极和沿第一方向布置的字线之间的选择晶体管共享的选择栅极。每条字线通常连接到沿第二方向布置的控制门。

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