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11. 发明授权

US5109499A Vector multiprocessor system which individually indicates the data element stored in common vector register 失效
标题翻译：矢量多处理器系统，分别指示存储在公共矢量寄存器中的数据元素
公开(公告)号：US5109499A
公开(公告)日：1992-04-28
申请号：US237418
申请日：1988-08-29
申请人： Yasuhiro Inagami , Yoshiko Tamaki , Katsuyoshi Kitai
发明人： Yasuhiro Inagami , Yoshiko Tamaki , Katsuyoshi Kitai
IPC分类号： G06F15/16 , G06F9/30 , G06F9/315 , G06F9/52 , G06F15/163 , G06F15/167 , G06F15/177 , G06F15/78 , G06F15/80 , G06F17/16
CPC分类号： G06F9/30032 , G06F15/8084 , G06F15/8092 , G06F9/30036 , G06F9/30109
摘要： At least one common vector register capable of being accessed from a plurality of vector processors constituting the multiprocessor is provided in order to transfer vector data among the vector processors at a high speed. The common vector register includes data fields each holding the value of vector data, access control sections provided corresponding to the respective data fields and showing the status of data access from the vector processor for synchronization of data sending and receiving, when the vector data is transferred among the different vector processors through the common vector register, and an access right section used for managing the number of the vector processor which is allowed to access the common vector register.
摘要翻译：提供能够从构成多处理器的多个向量处理器访问的至少一个公共向量寄存器，以便高速地在向量处理器之间传送向量数据。公共向量寄存器包括各自保存矢量数据值的数据字段，与各个数据字段对应地提供的访问控制部分，并且当矢量数据被传送时，显示来自矢量处理器的用于数据发送和接收同步的数据访问状态在通过公共向量寄存器的不同向量处理器中，以及用于管理允许访问公共向量寄存器的向量处理器的数量的访问权限部分。

12. 发明授权

US4992936A Address translation method and apparatus therefor 失效
标题翻译：地址转换方法及其设备
公开(公告)号：US4992936A
公开(公告)日：1991-02-12
申请号：US269058
申请日：1988-11-09
申请人： Hisashi Katada , Yasuhiro Inagami , Yoshiko Tamaki , Shigeo Nagashima
发明人： Hisashi Katada , Yasuhiro Inagami , Yoshiko Tamaki , Shigeo Nagashima
IPC分类号： G06F12/02 , G06F12/10
CPC分类号： G06F12/1009 , G06F2212/652
摘要： In a method and apparatus wherein a logical address of a main storage designated by a program is translated into a real address: an address translation table for each of a plurality of address translation sizes is prepared; the logical address designated by the program is fetched; an entry of an address translation table whose address translation size is larger than those of the other address translation tables among the plurality of address translation sizes is first identified based on the fetched logical address; a first information on an address translation size validity included in the first indentified entry is checked; address translation in units of translation size of the address translation table including the first identified entry is performed when the first information indicates valid; when the first information indicates invalid, an entry of an address translation table whose address translation size is next smaller than that of the address translation table including the first identified entry is second identified, based on the top address of the address translation table including the second identified entry and based on the fetched logical address; and address translation is further performed returning back to the above-mentioned step where the first information on the address translation size included in the first identified entry is checked.
摘要翻译：在将由程序指定的主存储器的逻辑地址转换为实际地址的方法和装置中，准备多个地址转换大小中的每一个的地址转换表; 获取程序指定的逻辑地址; 首先根据获取的逻辑地址来识别其地址转换大小大于多个地址转换大小中的其他地址转换表的地址转换表的条目; 检查包含在第一识别条目中的地址转换大小有效性的第一信息; 当第一信息表示有效时，执行包括第一识别条目的地址转换表的翻译大小单位的地址转换; 当第一信息指示无效时，基于包括第二信息的地址转换表的顶部地址，第二识别地址转换大小接下来小于包括第一标识条目的地址转换表的地址转换大小的条目的条目识别的条目并基于获取的逻辑地址; 进一步执行地址转换，返回上述步骤，其中检查包含在第一识别条目中的地址转换大小的第一信息。

13. 发明授权

US5440750A Information processing system capable of executing a single instruction for watching and waiting for writing of information for synchronization by another processor 失效
标题翻译：信息处理系统能够执行用于观看和等待另一个处理器同步的信息的写入的单个指令
公开(公告)号：US5440750A
公开(公告)日：1995-08-08
申请号：US643121
申请日：1991-01-18
申请人： Katsuyoshi Kitai , Yasuhiro Inagami , Yoshiko Tamaki , Yoshikazu Tanaka
发明人： Katsuyoshi Kitai , Yasuhiro Inagami , Yoshiko Tamaki , Yoshikazu Tanaka
IPC分类号： G06F15/16 , G06F9/30 , G06F9/46 , G06F11/16 , G06F15/177
CPC分类号： G06F9/52 , G06F9/30087
摘要： Each processor of a multiprocessor system which shares a main storage has a execution circuit for executing a compare and watch instruction provided for watching information for synchronization written into a main storage. When one program being executed by one of the processors issues an instruction, the circuit fetches information for synchronization from a location within the main storage designated by the instruction, compares that fetched information with another information designated by the instruction. If they do not have a specific relation, the fetching and the comparison is repeated. The circuit has a circuit for limiting the repetition with a limited number of times. The circuit further has a circuit for counting a total amount of CPU time spent for execution of plural watching instructions issued by the same program.
摘要翻译：共享主存储器的多处理器系统的每个处理器具有执行电路，用于执行提供用于观看同步信息的比较和观看指令，写入主存储器。当由一个处理器执行的一个程序发出指令时，电路从由指令指定的主存储器内的位置获取用于同步的信息，将获取的信息与该指令指定的另一个信息进行比较。如果它们没有特定关系，则重复获取和比较。该电路具有用于限制次数的重复的电路。该电路还具有用于计算用于执行由相同程序发出的多个观看指令所花费的CPU时间的总量的电路。

14. 发明授权

US5193186A Processor system for executing processes in parallel under multitask, control method of waiting for event of process 失效
标题翻译：用于在多任务下并行执行进程的处理器系统，等待进程事件的控制方法
公开(公告)号：US5193186A
公开(公告)日：1993-03-09
申请号：US647754
申请日：1991-01-30
申请人： Yoshiko Tamaki , Katsuyoshi Kitai , Yasuhiro Inagami , Yoshikazu Tanaka
发明人： Yoshiko Tamaki , Katsuyoshi Kitai , Yasuhiro Inagami , Yoshikazu Tanaka
IPC分类号： G06F15/16 , G06F9/46 , G06F9/52 , G06F15/177
CPC分类号： G06F9/52
摘要： In a processor system for executing a plurality of tasks, which respectively control execution of one or more of a plurality of processes, a method of restarting execution of a first process which is under control of a specific task being executed, after the first process is stopped to wait for occurrence of an event associated with at least one second process different from the first process, includes the steps of (a) detecting whether or not the event associated with the second process has occurred; (b) restarting the execution of the first process when it is detected that the event has occurred; (c) determining whether or not there is an execution waiting process when the event has not yet occurred; (d) executing an executing waiting process when there is any; and (e) repeating the steps (a) to (d) after execution of an execution waiting process when there is any or after the step (c) when there is not such an execution waiting process.
摘要翻译：在用于执行分别控制多个处理中的一个或多个处理的执行的多个任务的处理器系统中，在第一处理之后重新启动正在执行的特定任务正在执行的第一进程的执行的方法停止等待与与第一处理不同的至少一个第二进程相关联的事件的发生，包括以下步骤：（a）检测与第二进程相关联的事件是否已经发生; （b）当检测到事件发生时重新启动第一进程的执行; （c）当事件尚未发生时确定是否存在执行等待处理; （d）当有任何时候执行执行的等待进程; 以及（e）当在没有这样的执行等待处理时存在步骤（c）之后或之后执行执行等待处理之后，重复步骤（a）至（d）。

15. 发明授权

US4910667A Vector processor with vector buffer memory for read or write of vector data between vector storage and operation unit 失效
标题翻译：矢量处理器，带矢量缓冲存储器，用于在矢量存储和操作单元之间读取或写入矢量数据
公开(公告)号：US4910667A
公开(公告)日：1990-03-20
申请号：US184788
申请日：1988-04-22
申请人： Teruo Tanaka , Koichiro Omoda , Yasuhiro Inagami , Takayuki Nakagawa , Mamoru Sugie , Shigeo Nagashima
发明人： Teruo Tanaka , Koichiro Omoda , Yasuhiro Inagami , Takayuki Nakagawa , Mamoru Sugie , Shigeo Nagashima
IPC分类号： G06F12/08 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8053
摘要： In a vector processor having vector registers, a vector buffer storage for temporarily storing vector data is arranged closer to the vector registers than to a main storage, and a vector buffer storage control including an identification storage for storing identification information of the vector data stored at storage locations of the buffer storage and a check circuit for checking if the vector data identification information is in the identificatgion storage is provided. The vector buffer storage control checks if the identification information of the vector data designated by a vector data fetch instruction for the main storage is in the indentification storage, and if it is in the identification storage, it fetches the vector data from the buffer storage and transfers it to the vector register, and if it is not in the identification storage, it instructs to fetch the vector data from the main storage, transfers the vector data fetched from the main storage to the vector register and stores it into the buffer storage.
摘要翻译：在具有向量寄存器的向量处理器中，用于临时存储向量数据的向量缓冲存储器比向主存储器靠近向量寄存器布置，并且向量缓冲器存储控制包括用于存储存储在提供缓冲存储器的存储位置和用于检查矢量数据识别信息是否在识别存储器中的检查电路。向量缓冲存储控制检查由主存储器的矢量数据获取指令指定的矢量数据的识别信息是否在识别存储器中，并且如果它在识别存储器中，则从缓冲存储器中取出向量数据，将其传送到向量寄存器，如果不在识别存储器中，则指示从主存储器获取向量数据，将从主存储器获取的向量数据传送到向量寄存器，并将其存储到缓冲存储器中。

16. 发明授权

US4782441A Vector processor capable of parallely executing instructions and reserving execution status order for restarting interrupted executions 失效
标题翻译：能够平行执行指令并保留执行状态顺序的矢量处理器重新启动中断的执行
公开(公告)号：US4782441A
公开(公告)日：1988-11-01
申请号：US872396
申请日：1986-06-10
申请人： Yasuhiro Inagami , Shigeo Nagashima , Koichiro Omoda , Takayuki Nakagawa , Teruo Tanaka
发明人： Yasuhiro Inagami , Shigeo Nagashima , Koichiro Omoda , Takayuki Nakagawa , Teruo Tanaka
IPC分类号： G06F9/46 , G06F9/38 , G06F9/48 , G06F15/78 , G06F17/16 , G06F9/28 , G06F7/00
CPC分类号： G06F15/8053
摘要： In a processor such as a vector processor in which a plurality of data are processed by one instruction and a plurality of instructions are parallely processed, apparatus is provided for storing, during an interruption of the program currently being executed, the instructions being executed in the conceptual order of appearance in the program of the instruction being executed, and the sequential count of the sets of data processed. The stored information is used to restart the execution of the interrupted program at the appropriate point.
摘要翻译：在其中通过一个指令处理多个数据并且多个指令并行处理的诸如矢量处理器的处理器中，提供装置，用于在当前执行的程序的中断期间存储在正在执行的指令的程序中出现的概念顺序，以及处理的数据组的顺序计数。存储的信息用于在适当的点重新启动中断的程序的执行。

17. 发明授权

US6049839A Data processor with multiple register queues 失效
标题翻译：具有多个寄存器队列的数据处理器
公开(公告)号：US6049839A
公开(公告)日：2000-04-11
申请号：US172170
申请日：1993-12-23
申请人： Hiroaki Fujii , Yasuhiro Inagami , Shigeo Takeuchi
发明人： Hiroaki Fujii , Yasuhiro Inagami , Shigeo Takeuchi
IPC分类号： G06F9/34 , G06F9/30 , G06F9/38 , G06F13/00
CPC分类号： G06F9/30134 , G06F9/384
摘要： A data processor includes a register group having registers of the number larger than the number of registers which can be designated by a register specifier field of an instruction. The register group consists of a plurality of register queues with respect to logical register numbers designated in the instruction, each register queue including a plurality of physical registers. In the data processor, a physical register number forming section is provided for converting the logical register number to a physical register number in the register queue corresponding to the logical register number, by using queue control information designated in the register specifier field and read/write information decided by the kind of the instruction and the position of the register specifier field in the instruction.
摘要翻译：数据处理器包括具有比可由指令的寄存器说明符字段指定的寄存器数量大的寄存器的寄存器组。寄存器组包括相对于指令中指定的逻辑寄存器号的多个寄存器队列，每个寄存器队列包括多个物理寄存器。在数据处理器中，提供物理寄存器号码形成部分，用于通过使用寄存器说明符字段中指定的队列控制信息和读取/写入将逻辑寄存器号码转换为对应于逻辑寄存器号码的寄存器队列中的物理寄存器号码指令种类决定的信息和指令中寄存器说明符字段的位置。

18. 发明授权

US5729723A Data processing unit 失效
标题翻译：数据处理单元
公开(公告)号：US5729723A
公开(公告)日：1998-03-17
申请号：US275347
申请日：1994-07-15
申请人： Hideo Wada , Katsumi Takeda , Yasuhiro Inagami , Hiroaki Fujii
发明人： Hideo Wada , Katsumi Takeda , Yasuhiro Inagami , Hiroaki Fujii
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/46 , G06F3/00
CPC分类号： G06F9/381 , G06F9/30101 , G06F9/30127 , G06F9/30138 , G06F9/462
摘要： A data processing unit which can access a greater number of registers than registers addressable by an instruction to realize high-speed execution of a program. To this end, the data processing unit includes a greater number of floating point registers than the number of registers addressable by an ordinary instruction, a window start pointer register, a window start pointer valid register, a conversion circuit, when the window start pointer valid register has a value of 1, for converting a floating point register number in the instruction to a physical floating point register number and for changing a conversion pattern depending on the value of the window start pointer register, a window start pointer set instruction for setting a value at the window start pointer register, and floating point register pre-load and post-store instructions having a register field different in length from the ordinary instruction, and wherein the floating point register number specified by the register field is converted by the conversion circuit to the physical floating point register number on the basis of the value of the window start pointer register.
摘要翻译：一种数据处理单元，其可以访问比通过用于实现程序的高速执行的指令可寻址的寄存器的更多数量的寄存器。为此，数据处理单元包括比通过普通指令寻址的寄存器数量更多的浮点寄存器，窗口开始指针寄存器，窗口起始指针有效寄存器，转换电路，当窗口起始指针有效时寄存器的值为1，用于将指令中的浮点寄存器号转换为物理浮点寄存器号，并根据窗口开始指针寄存器的值改变转换模式;窗口开始指针集指令，用于设置窗口开始指针寄存器的值，以及具有与普通指令长度不同的寄存器字段的浮点寄存器预加载和后存储指令，并且其中由寄存器字段指定的浮点寄存器号由转换电路基于窗口起始指针寄存器的值，到物理浮点寄存器号。

19. 发明授权

US5581721A Data processing unit which can access more registers than the registers indicated by the register fields in an instruction 失效
标题翻译：数据处理单元可以访问比指令中的寄存器字段指示的寄存器更多的寄存器
公开(公告)号：US5581721A
公开(公告)日：1996-12-03
申请号：US600155
申请日：1996-02-12
申请人： Hideo Wada , Katsumi Takeda , Yasuhiro Inagami , Hiroaki Fujii
发明人： Hideo Wada , Katsumi Takeda , Yasuhiro Inagami , Hiroaki Fujii
IPC分类号： G06F9/38 , G06F9/30 , G06F9/46 , G06F17/16 , G06F12/00
CPC分类号： G06F9/30127 , G06F9/3013 , G06F9/384 , G06F9/462
摘要： The data processing unit includes a greater number of physical floating point registers than the number of floating point registers accessible by an instruction, window start point register having a plurality of bits, 1-bit window start pointer valid register, conversion apparatus for converting a floating point register number in an instruction to a physical floating point register number when the value of the window start pointer valid register is 1, and changing the pattern of this conversion by a value obtained from the value of the window start pointer register or the value of a window stride designated in a specific instruction, and the value of the window start pointer register. Also provided is an instruction controller for detecting a window start pointer set instruction for setting a value to the window start pointer register, a floating point register pre-load instruction for converting the floating point register number in the instruction to a physical floating point register number by the conversion circuit from the value obtained from the value of the window start pointer register and the value of the window stride, and storing a main memory data in the physical floating point register indicated by the physical floating point register number.
摘要翻译：数据处理单元包括比指令可访问的浮点寄存器数量多的物理浮点寄存器数量，具有多个位的窗口起始点寄存器，1位窗口开始指针有效寄存器，用于转换浮点数的转换装置当窗口开始指针有效寄存器的值为1时，在物理浮点寄存器编号的指令中指定点寄存器号，并且通过从窗口开始指针寄存器的值获得的值来改变该转换的模式，在特定指令中指定的窗口步长，以及窗口起始指针寄存器的值。还提供了一种用于检测用于将窗口开始指针寄存器的值设置的窗口开始指针集指令的指令控制器，用于将指令中的浮点寄存器号转换为物理浮点寄存器号的浮点寄存器预加载指令通过转换电路根据从窗口开始指针寄存器的值和窗口步幅获得的值，并将主存储器数据存储在由物理浮点寄存器号表示的物理浮点寄存器中。

20. 发明授权

US5349653A Apparatus for converting parallel bits of an electrical data signal into serial bits of an optical data signal utilizing an optical time delay 失效
标题翻译：用于使用光时延将电数据信号的并行位转换为光数据信号的串行位的装置
公开(公告)号：US5349653A
公开(公告)日：1994-09-20
申请号：US775030
申请日：1991-10-11
申请人： Hiroshi Kurokawa , Yasushi Takahashi , Yasuhiro Inagami
发明人： Hiroshi Kurokawa , Yasushi Takahashi , Yasuhiro Inagami
IPC分类号： H03M9/00 , G06F5/00
CPC分类号： H03M9/00
摘要： A plurality of electric data signals representing parallel data bits are applied to a plurality of gates or control terminals on-off controlling optical switches, respectively. A single pulsed synchronizing signal is distributed to input terminals of the plurality of gates or the optical switches. Synchronizing signals, which have passed through gates or optical switches, which are in an ON state, among the plurality of gates or the optical switches are coupled to synchronize finally an optical signal. In this way a serial optical pulsed output signal can be obtained by utilizing optical delay in a process for distributing the synchronizing signals or a process for coupling the synchronizing signals.
摘要翻译：表示并行数据位的多个电数据信号分别被施加到多个门或控制端开关控制光开关。单个脉冲同步信号被分配到多个门或光开关的输入端。多个门或光开关之中已经通过栅极或光开关的处于ON状态的同步信号被耦合以使光信号最终同步。以这种方式，可以通过在用于分配同步信号的处理中利用光学延迟或者用于耦合同步信号的处理来获得串行光脉冲输出信号。

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