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11. 发明授权

US07514322B2 Shielded gate field effect transistor 有权
标题翻译：屏蔽栅场效应晶体管
公开(公告)号：US07514322B2
公开(公告)日：2009-04-07
申请号：US12125242
申请日：2008-05-22
申请人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
发明人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
IPC分类号： H01L21/336 , H01L23/62
CPC分类号： H01L29/7813 , H01L21/26513 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/66666 , H01L29/66712 , H01L29/66727 , H01L29/66734 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A FET includes a trench in a semiconductor region. The trench has a lower portion with a shield electrode therein, and an upper portion with a gate electrode therein, where the upper portion is wider than the lower portion. The semiconductor region includes a substrate of a first conductivity type and a first silicon region of a second conductivity type over the substrate. The first silicon region has a first portion extending to a depth intermediate top and bottom surfaces of the gate electrode. The first silicon region has a second portion extending to a depth intermediate top and bottom surfaces of the shield electrode. The semiconductor region further includes a second silicon region of the first conductivity type between the lower trench portion and the second portion of the first silicon region that has a laterally-graded doping concentration decreasing in a direction away from the sidewalls of the lower trench portion.
摘要翻译： FET包括半导体区域中的沟槽。沟槽中具有屏蔽电极的下部以及其中具有栅电极的上部，其中上部比下部更宽。半导体区域包括在衬底上的第一导电类型的衬底和第二导电类型的第一硅区域。第一硅区域具有延伸到栅极电极顶部和底部表面深度的第一部分。第一硅区域具有延伸到屏蔽电极顶部和底部表面深度的第二部分。半导体区域还包括第一导电类型的第二硅区域，在第一硅区域的下沟槽部分和第二部分之间具有横向渐变的掺杂浓度，其沿远离下沟槽部分的侧壁的方向减小。

12. 发明申请

US20080258213A1 Shielded Gate Field Effect Transistor 有权
标题翻译：屏蔽栅场效应晶体管
公开(公告)号：US20080258213A1
公开(公告)日：2008-10-23
申请号：US12125242
申请日：2008-05-22
申请人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
发明人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/26513 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/66666 , H01L29/66712 , H01L29/66727 , H01L29/66734 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A FET includes a trench in a semiconductor region. The trench has a lower portion with a shield electrode therein, and an upper portion with a gate electrode therein, where the upper portion is wider than the lower portion. The semiconductor region includes a substrate of a first conductivity type and a first silicon region of a second conductivity type over the substrate. The first silicon region has a first portion extending to a depth intermediate top and bottom surfaces of the gate electrode. The first silicon region has a second portion extending to a depth intermediate top and bottom surfaces of the shield electrode. The semiconductor region further includes a second silicon region of the first conductivity type between the lower trench portion and the second portion of the first silicon region that has a laterally-graded doping concentration decreasing in a direction away from the sidewalls of the lower trench portion.
摘要翻译： FET包括半导体区域中的沟槽。沟槽中具有屏蔽电极的下部以及其中具有栅电极的上部，其中上部比下部更宽。半导体区域包括在衬底上的第一导电类型的衬底和第二导电类型的第一硅区域。第一硅区域具有延伸到栅极电极顶部和底部表面深度的第一部分。第一硅区域具有延伸到屏蔽电极顶部和底部表面深度的第二部分。半导体区域还包括第一导电类型的第二硅区域，在第一硅区域的下沟槽部分和第二部分之间具有横向渐变的掺杂浓度，其沿远离下沟槽部分的侧壁的方向减小。

13. 发明申请

US20100258855A1 Field Effect Transistor with Self-aligned Source and Heavy Body Regions and Method of Manufacturing Same 有权
标题翻译：具有自对准源和重体区域的场效应晶体管及其制造方法相同
公开(公告)号：US20100258855A1
公开(公告)日：2010-10-14
申请号：US12822008
申请日：2010-06-23
申请人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
发明人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
IPC分类号： H01L27/088 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/26513 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/66666 , H01L29/66712 , H01L29/66727 , H01L29/66734 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches include a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.
摘要翻译：场效应晶体管包括延伸到第一导电类型的半导体区域的多个沟槽。多个沟槽包括多个门控沟槽和多个非门控沟槽。第二导电体的主体区域在相邻沟槽之间的半导体区域中延伸。电介质材料填充每个门控沟槽和非门控沟槽的底部。栅极电极设置在每个门控沟槽中。第二导电类型的导电材料设置在每个非门控沟槽中，使得导电材料并且沿着非门控沟槽的侧壁接触对应的主体区域。

14. 发明申请

US20100038708A1 Method and Structure for Forming a Shielded Gate Field Effect Transistor 有权
标题翻译：用于形成屏蔽栅场效应晶体管的方法和结构
公开(公告)号：US20100038708A1
公开(公告)日：2010-02-18
申请号：US12582487
申请日：2009-10-20
申请人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
发明人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/26513 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/66666 , H01L29/66712 , H01L29/66727 , H01L29/66734 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a charge balance MOSFET includes the following steps. A substrate with an overlying epitaxial layer both of a first conductivity type, are provided. A gate trench extending through the epitaxial layer and terminating within the substrate is formed. A shield dielectric lining sidewalls and bottom surface of the gate trench is formed. A shield electrode is formed in the gate trench. A gate dielectric layer is formed along upper sidewalls of the gate trench. A gate electrode is formed in the gate trench such that the gate electrode extends over but is insulated from the shield electrode. A deep dimple extending through the epitaxial layer and terminating within the substrate is formed such that the deep dimple is laterally spaced from the gate trench. The deep dimple is filled with silicon material of the second conductivity type.
摘要翻译：形成电荷平衡MOSFET的方法包括以下步骤。提供了具有第一导电类型的上覆外延层的衬底。形成延伸穿过外延层并终止在衬底内的栅极沟槽。形成栅极沟槽的侧壁和底表面的屏蔽电介质。在栅极沟槽中形成屏蔽电极。栅极电介质层沿栅极沟槽的上侧壁形成。栅电极形成在栅极沟槽中，使得栅电极延伸过去但与屏蔽电极绝缘。形成延伸穿过外延层并终止于衬底内的深凹坑，使得深凹坑与栅沟槽横向间隔开。深凹坑填充有第二导电类型的硅材料。

15. 发明授权

US07625799B2 Method of forming a shielded gate field effect transistor 有权
标题翻译：形成屏蔽栅场效应晶体管的方法
公开(公告)号：US07625799B2
公开(公告)日：2009-12-01
申请号：US12418949
申请日：2009-04-06
申请人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
发明人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
IPC分类号： H01L21/336 , H01L23/62
CPC分类号： H01L29/7813 , H01L21/26513 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/66666 , H01L29/66712 , H01L29/66727 , H01L29/66734 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor region with an epitaxial layer extending over the semiconductor region is provided. A first silicon etch is performed to form an upper trench portion extending into and terminating within the epitaxial layer. A protective material is formed extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion. A second silicon etch is performed to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the semiconductor region, such that the lower trench portion is narrower than the upper trench portion. A two-pass angled implant of dopants of the first conductivity type is carried out to form a silicon region of first conductivity type along sidewalls of the lower trench portion, while the protective material blocks the implant dopants from entering the sidewalls of the upper trench portion and the mesa region adjacent the upper trench portion.
摘要翻译：提供了具有在半导体区域上延伸的外延层的半导体区域。执行第一硅蚀刻以形成延伸到外延层内并在外延层内终止的上沟槽部分。沿着上沟槽部分的侧壁以及与上沟槽部分相邻的台面区域，而不是沿着上沟槽部分的底表面延伸形成保护材料。执行第二硅蚀刻以形成从上沟槽部分的底表面延伸穿过外延层并终止在半导体区域内的下沟槽部分，使得下沟槽部分比上沟槽部分窄。执行第一导电类型的掺杂剂的双向成角度注入，以形成沿着下沟槽部分的侧壁的第一导电类型的硅区域，而保护材料阻挡注入掺杂剂进入上沟槽部分的侧壁以及与上沟槽部分相邻的台面区域。

16. 发明申请

US20090191678A1 Method of Forming a Shielded Gate Field Effect Transistor 有权
标题翻译：形成屏蔽栅场效应晶体管的方法
公开(公告)号：US20090191678A1
公开(公告)日：2009-07-30
申请号：US12418949
申请日：2009-04-06
申请人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
发明人： Hamza Yilmaz , Daniel Calafut , Steven Sapp , Nathan Kraft , Ashok Challa
IPC分类号： H01L21/334
CPC分类号： H01L29/7813 , H01L21/26513 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/66666 , H01L29/66712 , H01L29/66727 , H01L29/66734 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor region with an epitaxial layer extending over the semiconductor region is provided. A first silicon etch is performed to form an upper trench portion extending into and terminating within the epitaxial layer. A protective material is formed extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion. A second silicon etch is performed to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the semiconductor region, such that the lower trench portion is narrower than the upper trench portion. A two-pass angled implant of dopants of the first conductivity type is carried out to form a silicon region of first conductivity type along sidewalls of the lower trench portion, while the protective material blocks the implant dopants from entering the sidewalls of the upper trench portion and the mesa region adjacent the upper trench portion.
摘要翻译：提供了具有在半导体区域上延伸的外延层的半导体区域。执行第一硅蚀刻以形成延伸到外延层内并在外延层内终止的上沟槽部分。沿着上沟槽部分的侧壁以及与上沟槽部分相邻的台面区域，而不是沿着上沟槽部分的底表面延伸形成保护材料。执行第二硅蚀刻以形成从上沟槽部分的底表面延伸穿过外延层并终止在半导体区域内的下沟槽部分，使得下沟槽部分比上沟槽部分窄。执行第一导电类型的掺杂剂的双向成角度注入以在下沟槽部分的侧壁形成第一导电类型的硅区域，而保护材料阻挡注入掺杂剂进入上沟槽部分的侧壁以及与上沟槽部分相邻的台面区域。

17. 发明申请

US20070155104A1 Power device utilizing chemical mechanical planarization 失效
标题翻译：利用化学机械平面化的功率器件
公开(公告)号：US20070155104A1
公开(公告)日：2007-07-05
申请号：US11327657
申请日：2006-01-05
申请人： Bruce Marchant , Thomas Grebs , Rodney Ridley , Nathan Kraft
发明人： Bruce Marchant , Thomas Grebs , Rodney Ridley , Nathan Kraft
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/7811 , H01L21/3083 , H01L29/0696 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/7813 , Y10S438/942 , Y10S438/95
摘要： A trench-gated field effect transistor (FET) is formed as follows. Using one mask, a plurality of active gate trenches and at least one gate runner trench are defined and simultaneously formed in a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench.
摘要翻译：沟槽门控场效应晶体管（FET）如下形成。使用一个掩模，多个有源栅极沟槽和至少一个栅极流道沟槽被限定并同时形成在硅区域中，使得（i）至少一个栅极流道沟槽的宽度大于多个栅极沟槽的宽度的有源栅极沟槽，以及（ii）多个有源栅极沟槽与至少一个栅极流道沟槽邻接。

18. 发明申请

US20070173021A1 Self-aligned trench MOSFET structure and method of manufacture 有权
标题翻译：自对准沟槽MOSFET结构及其制造方法
公开(公告)号：US20070173021A1
公开(公告)日：2007-07-26
申请号：US11339998
申请日：2006-01-25
申请人： Christopher Kocon , Nathan Kraft
发明人： Christopher Kocon , Nathan Kraft
IPC分类号： H01L21/336
CPC分类号： H01L29/7811 , H01L29/0661 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： PATENT A trench gate FET is formed as follows. A well region is formed in a silicon region. A plurality of active gate trenches and a termination trench are simultaneously formed in an active region and a termination region of the FET, respectively, such that the well region is divided into a plurality of active body regions and a termination body region. Using a mask, openings are formed over the termination body region and the active body region. Dopants are implanted into the active body regions and the termination body region through the openings thereby forming a first region in each active and termination body region. Exposed surfaces of all first regions are recessed so as to form a bowl-shaped recess having slanted walls and a bottom protruding through the first region such that remaining portions of the first region in each active body region form source regions that are self-aligned to the active gate trenches.
摘要翻译：沟道栅FET如下形成。阱区域形成在硅区域中。多个有源栅极沟槽和端接沟槽分别同时形成在FET的有源区域和端接区域中，使得阱区域被分成多个有源体区域和端接体区域。使用掩模，在终端体区域和活动体区域上形成开口。通过开口将掺杂剂注入活性体区域和终端体区域，从而在每个活性和终止体区域中形成第一区域。所有第一区域的露出的表面是凹进的，从而形成具有倾斜壁和通过第一区域突出的底部的碗状凹部，使得每个活性体区域中的第一区域的剩余部分形成自对准的源区域有源栅极沟槽。

19. 发明申请

US20080064168A1 Method for Forming a Shielded Gate Trench FET with the Shield and Gate Electrodes Being Connected Together 有权
标题翻译：用于形成屏蔽栅极沟道FET的方法，其中屏蔽和栅电极连接在一起
公开(公告)号：US20080064168A1
公开(公告)日：2008-03-13
申请号：US11938583
申请日：2007-11-12
申请人： Nathan Kraft , Christopher Kocon , Paul Thorup
发明人： Nathan Kraft , Christopher Kocon , Paul Thorup
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/823437 , H01L27/088 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L29/7811
摘要： A method of forming a field effect transistor includes the following steps. A trench is formed in a semiconductor region, and a shield dielectric layer lining lower sidewalls and a bottom surface of the trench is formed. A shield electrode is formed in a lower portion of the trench, and a dielectric layer is formed along upper trench sidewalls and over the shield electrode. A gate electrode is formed in the trench over the shield electrode, and an interconnect layer connecting the gate electrode and the shield electrode is formed.
摘要翻译：形成场效应晶体管的方法包括以下步骤。在半导体区域中形成沟槽，并形成衬套下侧壁和沟槽底面的屏蔽电介质层。屏蔽电极形成在沟槽的下部，并且沿上沟槽侧壁和屏蔽电极上方形成电介质层。在屏蔽电极上的沟槽中形成栅电极，形成连接栅电极和屏蔽电极的互连层。

20. 发明申请

US20110204436A1 Shielded Gate Trench FET with the Shield and Gate Electrodes Connected Together in Non-active Region 审中-公开
标题翻译：屏蔽栅沟槽FET，屏蔽和栅极电极一起连接在非有源区域
公开(公告)号：US20110204436A1
公开(公告)日：2011-08-25
申请号：US12978824
申请日：2010-12-27
申请人： Nathan Kraft , Christopher Boguslaw Kocon , Paul Thorup
发明人： Nathan Kraft , Christopher Boguslaw Kocon , Paul Thorup
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/823437 , H01L27/088 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L29/7811
摘要： A field effect transistor (FET) in a semiconductor die including an active region housing active cells, a non-active region with no active cells therein, a drift region of a first conductivity type, a body region of a second conductivity type over the drift region, and a plurality of trenches extending through the body region and into the drift region. Each trench includes a shield electrode and a gate electrode, the shield electrode being disposed below the gate electrode. The FET further includes source regions of the first conductivity type in the body region adjacent to each trench, heavy body regions of the second conductivity type in the body regions adjacent the source regions, and a source interconnect layer contacting the source regions and heavy body regions. The shield electrode and the gate electrode extend out of each trench and into the non-active region where the shield electrode and gate electrode are electrically connected together by a gate interconnect layer.
摘要翻译：半导体管芯中的场效应晶体管（FET），其包括容纳有源电池的有源区域，其中没有有源电池的非有源区域，第一导电类型的漂移区域，漂移区域上的第二导电类型的体区域以及延伸穿过身体区域并进入漂移区域的多个沟槽。每个沟槽包括屏蔽电极和栅电极，屏蔽电极设置在栅电极下方。 FET还包括与每个沟槽相邻的主体区域中的第一导电类型的源极区域，与源极区域相邻的体区域中的第二导电类型的重体区域和与源区域和重体区域接触的源极互连层。屏蔽电极和栅电极延伸出每个沟槽并进入非屏蔽电极和栅电极通过栅极互连层电连接在一起的非有源区。

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