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11. 发明专利

JPS634066A BIAS SPUTTERING DEVICE 失效
公开(公告)号：JPS634066A
公开(公告)日：1988-01-09
申请号：JP14690986
申请日：1986-06-25
申请人： HITACHI LTD
发明人： HORIUCHI MITSUAKI , TSUNEOKA MASATOSHI , OWADA NOBUO
IPC分类号： H01L21/285 , C23C14/54
摘要： PURPOSE:To form a film having good adhesiveness on a substrate surface without deteriorating film quality by detecting substrate current and providing a controller to control the density of the plasma generated near the substrate based on the detected current. CONSTITUTION:The inside of a chamber 1 is evacuated to a high vacuum by a discharge port 8 and gaseous Ar is introduced through a gas supply port 7 into the chamber until the prescribed degree of vacuum is attained. While an upper electrode 2 is heated by a heater 12, electric power is impressed from a negative power source 5 to a lower electrode 3 and electric power is also impressed simultaneously to the upper electrode 2 from a negative power source 4 to set the electrode at a required bias. The plasma is thereby generated between the two electrodes 2 and 3 and sputters a target T, thus forming the film on the surface of a substrate W. The current at the upper electrode 2 is measured by an ammeter 10 and a controller 11 makes the feedback control of the electric power of the negative power source 5 based on the measured value so that the current value attains approximately the prescribed value or above. While the bias at the upper electrode 2 is thereby held constant, the plasma density is controlled and the quantity of the ions flowing to the substrate W is increased.

12. 发明专利

JPS61125014A Semiconductor device and manufacture thereof 失效
标题翻译：半导体器件及其制造
公开(公告)号：JPS61125014A
公开(公告)日：1986-06-12
申请号：JP24598384
申请日：1984-11-22
申请人： Hitachi Ltd
发明人： OWADA NOBUO , HORIUCHI MITSUAKI , TSUNEOKA MASATOSHI
IPC分类号： H01L21/3205 , H01L21/28
CPC分类号： H01L21/28
摘要： PURPOSE:To prevent the lowering of a heat resistance, by forming an insulating wall in the peripheral portion of a hole wherein a metal silicide layer is formed, and by forming the lateral side of the insulating wall to be a gentle slope. CONSTITUTION:A field insulating film 2 and a gate insulating film 3 are formed on the main surface of a silicon substrate 1, then a gate electrode 4 is formed by patterning, and N source-drain regions 5 are formed. Then, an interlayer insulating film 6 is formed on the entire surface by deposition, and holes 7 are formed. Next, a platinum film 8 is formed on the entire surface by evaporation, heat treatment is applied thereto to form platinum silicide layers 9 are formed on a contacting interface with the silicon substrate 1, and thereafter the platinum film 8 is removed. Then, an insulating film 10 is formed on the entire surface by deposition, and a reactive ion etching is applied to remove the insulating film 8 on a flat portion. Then the film 10 is left as insulating walls 11 only on the peripheral portions of the holes 7, and the lateral sides 11a thereof are formed into gentle slopes. Subsequently, an SiO2 thin film 9a is removed and Al wirings 12 are formed. Thereby a contact of the silicon substrate with the Al wirings is avoided, and thus the lowering of a heat resistance can be prevented.
摘要翻译：目的：为了防止耐热性的降低，通过在形成金属硅化物层的孔的周边部分中形成绝缘壁，并且通过将绝缘壁的侧面形成为平缓的斜面。构成：在硅衬底1的主表面上形成场绝缘膜2和栅极绝缘膜3，然后通过图案化形成栅电极4，形成N +个源极 - 漏极区5。然后，通过沉积在整个表面上形成层间绝缘膜6，并且形成孔7。接下来，通过蒸发在整个表面上形成铂膜8，在与硅衬底1的接触界面上形成铂处理以形成铂硅化物层9，然后除去铂膜8。然后，通过沉积在整个表面上形成绝缘膜10，并且施加反应离子蚀刻以在平坦部分上去除绝缘膜8。然后，膜10仅作为绝缘壁11留在孔7的周边部分上，并且其侧边11a形成平缓的斜面。随后，除去SiO 2薄膜9a，形成Al布线12。由此，避免了硅衬底与Al布线的接触，从而可以防止耐热性的降低。

13. 发明专利

JPH01191443A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH01191443A
公开(公告)日：1989-08-01
申请号：JP1443988
申请日：1988-01-27
申请人： HITACHI LTD
发明人： AKIMORI HIROYUKI , HORIUCHI MITSUAKI , TSUNEOKA MASATOSHI , TOKUNAGA TAKAFUMI
IPC分类号： H01L21/3213 , H01L21/768
摘要： PURPOSE:To improve the step coverage of wirings in a connecting hole, by forming the connecting hole having a plurality of staircase-shaped steps around the entire inner wall of the connecting hole in a multilayer interconnection, and forming a wiring metal film in a bias sputtering method. CONSTITUTION:Conventional steps such as formations of an embedded layer 2 and a channel stopper region 5 are performed in the surface of a semiconductor substrate 1. An aluminum film is formed on the entire surface. The film is patterned, and a first wiring layer 10 is formed. Then, an interlayer insulating film 11 is formed on the entire surface. Thereafter, photoresist 14 having a specified shape is formed at a position which is to become a connecting hole 11a for a multilayer interconnection. With the photoresist as a mask, the insulating film 11 undergoes dry etching. Then, the resist 14 is brought back by plasma ashing, and the thickness is also reduced. With the resist 14 as a mask, the insulating film 11 undergoes dry etching again, and the connecting hole 11a having a staircase shaped inner wall is formed. After the resist 14 is removed, a second wiring layer 12 and an insulating film 13 are formed, and bipolar LSI is obtained.

14. 发明专利

JPS6453561A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6453561A
公开(公告)日：1989-03-01
申请号：JP21081887
申请日：1987-08-25
申请人： HITACHI LTD
发明人： TOKUNAGA TAKAFUMI , TSUNEOKA MASATOSHI , MIZUKAMI KOICHIRO
IPC分类号： H01L21/3205 , H01L21/3213 , H01L21/768 , H01L23/52 , H01L23/532
摘要： PURPOSE:To prevent a copper film from being oxidized, by employing a series of processes in which a photoresist pattern is etched away using an oxygen plasma process, and an anti-oxidation film is then etched using an etching mask, the copper film being thereafter etched using said etched anti-oxidation film as a mask. CONSTITUTION:Metal silicide films 20a, 20b and 20c are respectively formed on a base drawing electrode 13, a polycrystalline silicon emitter electrode 14 and a collector drawing area 9 in openings 21a, 21b and 21c, a TiN film 22 is thereafter formed. Next, a copper film 42 is formed on the TiN film 22, and an anti-oxidation film 24, such as a TiN film, is then formed on the copper film 42. Moreover, a film 43 for forming an etching mask, such as an aluminum film, is formed on the anti-oxidation film 24. Subsequently, a photoresist pattern 44 is formed in a predetermined shape on the film 43. Next, using, for example, a chlorine series etching gas, the film 43 is etched through the photoresist pattern 44 as a mask to form etching masks 45a, 45b and 45c. The photoresist pattern 44 is thereafter etched away using an oxygen plasma process. Accordingly, the copper film 42 can be effectively prevented from being oxidized.

15. 发明专利

JPS6329504A BIAS SPUTTERING 失效
公开(公告)号：JPS6329504A
公开(公告)日：1988-02-08
申请号：JP17157986
申请日：1986-07-23
申请人： HITACHI LTD
发明人： TSUNEOKA MASATOSHI , OWADA NOBUO , HORIUCHI MITSUAKI
IPC分类号： H01L21/285 , H01L21/3205
摘要： PURPOSE:To obtain a bias sputtering method capable of making the coating property of a film to be formed excellent without causing the decrease of film quality, by forming a bias sputtering film applying a treatment gas having specific gravity larger than argon gas. CONSTITUTION:On the upper part of a chamber 1, a gas supplying port 7 connecting to a treatmint gas source 6 is arranged. For the treatment gas source 6, the following are adopted, krypton gas, xenon gas and radon gas having specific gravity larger than argon gas, or a mixed gas of thease gases and argon gas. The treatment gas is introduced into the chamber 1, whose inside is kept a vacuum of about 1-100 Torr, and electric power is supplied to a lower electrode 3 from a negative power source 5, while an upper electrode 2 is heated by a heater 12. As the result, the surface coating of a silicon wafer W is completed by the effect of plasma generating in the vicinity of the upper electrode 2. As the gas having specified gravity larger than argon gas is used, the acceleration which moves the treatment gas toward the wafer W is decreased. Therefore, the generation of voids can be restrained and the film quality is improved.

16. 发明专利

JPS634062A BIAS SPUTTERING DEVICE 失效
公开(公告)号：JPS634062A
公开(公告)日：1988-01-09
申请号：JP14690786
申请日：1986-06-25
申请人： HITACHI LTD
发明人： HORIUCHI MITSUAKI , OWADA NOBUO , TSUNEOKA MASATOSHI
IPC分类号： H01L21/285 , C23C14/34 , C23C14/35
摘要： PURPOSE:To form a film having good quality and good adhesiveness with a bias sputtering device for executing sputtering by impression of a bias voltage to a substrate to be formed with the film by disposing a magnet near the substrate. CONSTITUTION:Gaseous Ar is introduced into a vacuum vessel 1 of the bias sputtering device and while an upper electrode 2 mounted with the Si wafer substrate W is heated by a heater 12, a negative voltage is impressed thereto by a power source 4 and the negative voltage is simultaneously impressed by a power source 5 to a lower electrode 3 provided with the magnet 13 as well to set a required bias. Plasma is thereby generated near the lower electrode 3 between the two electrodes 2 and 3 and Al atoms are driven out of an Al target T on the lower electrode 3 by the effect thereof. The Al atoms stick to the Si wafer W on the upper electrode 2. The permanent magnet 14 or the electromagnet to permit current regulation is provided near the upper electrode 2 to generate the plasma and the density thereof is increased, by which the Al film having the good adhesiveness even to the pattern having a large aspect ratio is deposited on the substrate W.

17. 发明专利

JPS60245263A CIRCUIT PROTECTION DEVICE 失效
公开(公告)号：JPS60245263A
公开(公告)日：1985-12-05
申请号：JP10047784
申请日：1984-05-21
申请人： HITACHI LTD
发明人： TSUNEOKA MASATOSHI
IPC分类号： H01L21/822 , H01L21/60 , H01L23/31 , H01L23/522 , H01L27/04 , H01L29/41
摘要： PURPOSE:To contrive the improvement in reliability by blocking the penetration of contaminants such as alkaline metal ions from the input terminal part and the output terminal part by a method wherein a semiconductor device is coated with an insulation protector from the input terminal to the output terminal and then provided with conductors on the input side and the output side, respectively. CONSTITUTION:The whole surface is coated with a passivation film 3 by including each pad part 1, and a recess is formed in the surface of the passivation film 3 on each pad part 1. An Al layer 5 is evaporated in this recess, and a capacitor whose one electrode is the pad 1 and other electrode is the Al layer 5 formed at the part of each pad 1. This manner eliminates the exposure of the pad part into the atmosphere because all the pads 1 are completely coated with the passivation film 3, and contaminants can be blocked from penetrating inside from the part of the pad 1. Therefore, an LSI chip can be prevented from contamination, and the improvement in reliability can be realized.

18. 发明专利

JPH051616B2 失效
公开(公告)号：JPH051616B2
公开(公告)日：1993-01-08
申请号：JP14633083
申请日：1983-08-12
申请人： HITACHI LTD
发明人： TSUNEOKA MASATOSHI
IPC分类号： H01L21/60 , H05K3/34

19. 发明专利

JPH0232543A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0232543A
公开(公告)日：1990-02-02
申请号：JP18286588
申请日：1988-07-22
申请人： HITACHI LTD
发明人： OWADA NOBUO , HORIUCHI MITSUAKI , OKUYA KEN , TSUNEOKA MASATOSHI
IPC分类号： H01L23/52 , H01L21/203 , H01L21/3205
摘要： PURPOSE:To enable an Al wiring to be highly reliable and achieve low resistance by forming a first wiring layer in a laminated structure of Al and a barrier metal and without adding an alloy element to an Al constituting other wiring layers formed above it. CONSTITUTION:A first interlayer insulation film 5 is formed at the upper layer of a first wiring layer 3. A second wiring layer 6 is pattern-formed at the upper layer of this insulation layer 5, and it is electrically connected to the wiring layer 3 through a through hole 7. This wiring layer 6 consists of a single-layer structure such as a pure Al without adding an alloy element such as Cu and Si and the specific resistance is lower than that of an Al wiring where the alloy element is added. After the pure Al film is coated on the surface of the interlayer insulation film 5 by the bias sputter method, the Al film is patterned by etching using a photoresist mask. In this case, substrate bias voltage is controlled so that the orientation strength (111) of a crystal grain becomes the maximum, thus preventing electromigration resistance of the wiring layer 6 from being reduced.

20. 发明专利

JPS634063A BIAS SPUTTERING DEVICE 失效
公开(公告)号：JPS634063A
公开(公告)日：1988-01-09
申请号：JP14690886
申请日：1986-06-25
申请人： HITACHI LTD
发明人： TSUNEOKA MASATOSHI , HORIUCHI MITSUAKI , AKIMORI HIROYUKI , ASANO ISAMU , OWADA NOBUO
IPC分类号： H01L21/285 , C23C14/34
摘要： PURPOSE:To form a film having good quality and excellent adhesiveness without increasing a bias voltage by controlling the amt. of the ions to be generated from an ion generating source by the quantity of substrate current at the time of forming the film of a target material on a substrate by a bias sputtering method. CONSTITUTION:The inside of a vacuum vessel 1 is evacuated to a vacuum and gaseous Ar is introduced from a gas source 6 into the vessel. While an upper electrode 2 mounted with an Si wafer W as the substrate is heated by a heater 12, electric power is impressed from a negative power source 5 to a lower electrode 3. Electric power is simultaneously impressed to the upper electrode 2 as well from a negative power source 4 to set the same at a required bias. Plasma is generated between the two electrodes 2 and 3 and Al particles from the Al target T on the lower electrode 3 are deposited on the wafer W by the effect thereof. The current of the upper electrode 2 is measured by an ammeter 10 and is inputted to a controller 11 which feeds the current back to an ion generator 14 such as ECR to control the ion quantity near the upper electrode. The film having the good adhesiveness to the pattern having a large aspect ratio as well is thus formed while the bias of the upper electrode 2 is held constant.

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