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11. 发明专利

JPS62274334A DATA PROCESSOR 失效
公开(公告)号：JPS62274334A
公开(公告)日：1987-11-28
申请号：JP11723386
申请日：1986-05-23
申请人： HITACHI LTD
发明人： MATSUI SHIGESUMI , NAKAZAWA TAKUICHIROU , KAWASAKI IKUYA
IPC分类号： G06F7/00
摘要： PURPOSE:To speed up arithmetic processing including size conversion by generating an overflow signal by AND operation between the detection signal of a detecting circuit and the overflow output of an arithmetic operation unit. CONSTITUTION:The overflow signal OVF is generated by detecting one of bits corresponding to digits higher than the most significant digit bit of an output register R4 for data size conversion which consists of a smaller number of bits than the absolute value display data of the output signal of the arithmetic logical operation unit ALU being logic 1 when the absolute value display data is processed or by detecting the dissidence of even one of all of the bits corresponding to digits higher than the most significant digit bit on an output register R3 and the most significant digit bit of the register R3 when complementary number display data of '2' is processed. Thus, the overflow signal is generate directly and the arithmetic processing including the size conversion is speeded up.

12. 发明专利

JP2003132683A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003132683A
公开(公告)日：2003-05-09
申请号：JP2001324357
申请日：2001-10-23
申请人： HITACHI LTD
发明人： YAMAOKA MASANAO , ISHIBASHI KOICHIRO , MATSUI SHIGESUMI , OSADA KENICHI
IPC分类号： G11C11/41 , G11C5/14 , G11C11/34 , G11C11/413 , G11C11/417 , G11C11/418 , H01L29/94
摘要： PROBLEM TO BE SOLVED: To reduce power consumption in a standby state by reducing a leak current of a system LSI in which a memory is mixed. SOLUTION: A power source switch is provided in a logic circuit in a system LSI, a leak current is reduced by cutting off the switch at the time of standby. Simultaneously, in a SRAM circuit, a leak current is reduced by controlling a substrate bias.

13. 发明专利

JP2002049608A MICROPROCESSOR, INTERFACE UNIT, INTERFACE METHOD AND DATA MOVEMENT METHOD 失效
公开(公告)号：JP2002049608A
公开(公告)日：2002-02-15
申请号：JP2001156245
申请日：2001-05-25
申请人： HITACHI LTD
发明人： MATSUI SHIGESUMI , KAWASAKI IKUYA , NARITA SUSUMU , NEMOTO MASATO
IPC分类号： G06F13/12 , G06F3/08 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To provide a microprocessor, an interface unit, an interface method and a data movement method which are improved in usability. SOLUTION: The microprocessor has a system clock, and there are provided an interface unit, an address access unit, a PC card control means and an external clock means. The interface unit makes a memory and the PC card directly connectable to the microprocessor. The address access unit corresponds to the system clock changing from the first status to the second status in order to access an external address space. The PC card control means stores setup data of the PC card including a setup time for address signal control and a hold time for holding address signal. The external clock means is connected to the memory, and also the system clock is connected to be used for a synchronous DRAM(dynamic random access memory).

14. 发明专利

JPH10301659A MICROPROCESSOR 失效
公开(公告)号：JPH10301659A
公开(公告)日：1998-11-13
申请号：JP11054897
申请日：1997-04-28
申请人： HITACHI LTD , HITACHI CHIYOU LSI SYS KK
发明人： MATSUDA KENGO , KAWASAKI IKUYA , AKAO YASUSHI , MATSUI SHIGESUMI , YAMAMOTO MITSUTAKE , HASHIMOTO KOJI
IPC分类号： G06F1/32 , G06F1/04
摘要： PROBLEM TO BE SOLVED: To substantially reduce power consumption by disposing a circuit for dynamically shifting a circuit block without the need of an operation among the plural circuit blocks to a low power consumption state. SOLUTION: A clock stoppage control circuit 42 inside a memory management unit 4 monitors the high-order three bits of address signals on a logical address bus 8a and judges which one of a cache area and a non-cache area a central processing unit 1 accesses and whether or not a so-called fixed physical space accessible only by a physical address is accessed. Then, control signals are sent to a clock supply/interruption circuit 19 and the supply of clock signals to a cache controller 7 is stopped at the time of accessing the non-cache area. Also, at the time of accessing the fixed physical space, the supply of the clock signals to the control part 41 of an address conversion circuit for converting a logical address to the physical address is stopped.

15. 发明专利

JP2578182B2 失效
公开(公告)号：JP2578182B2
公开(公告)日：1997-02-05
申请号：JP27067088
申请日：1988-10-28
申请人： HITACHI LTD
发明人： MASUDA SATOSHI , KAWASAKI IKUYA , MATSUI SHIGESUMI
IPC分类号： G06F12/08 , G06F11/22 , G06F11/28 , G06F12/10 , G06F15/78

16. 发明专利

JPH07321635A SIGNAL TRANSMISSION CIRCUIT AND LOGIC CIRCUIT 失效
公开(公告)号：JPH07321635A
公开(公告)日：1995-12-08
申请号：JP13263894
申请日：1994-05-23
申请人： HITACHI LTD
发明人： MATSUI SHIGESUMI , IZAWA RYUICHI
IPC分类号： H01L21/8238 , H01L27/092 , H03K19/0175
摘要： PURPOSE:To reduce current consumption by speeding up signal propagation by limiting the amplitude of the signal a level limiter while providing a logic function and allowing no current to flow through a CMOS circuit when the level is limited. CONSTITUTION:In order to speed up the signal propagation and to reduce power consumption, a control circuit C1 having a level limiter function is provided between drain outputs in common connection respectively to differential MOSFETs Q1, Q3, and Q2, Q4. The level is controlled so that a level difference between output signals Out1, Out2 is made constant in the circuit C1, and it is detected to turn off a P-channel MOSFET Q5 and an N-channel MOSFET Q6 with switch control. Thus, when a level difference between the signals Out1, Out2 exceeds a small voltage, the control signal C11 is set to a high level and the signal C12 is set to a low level to turn off the Q5, Q6 thereby stopping the amplification by the Q1, Q3 and Q2, Q4.

17. 发明专利

JPH05241833A 失效
公开(公告)号：JPH05241833A
公开(公告)日：1993-09-21
申请号：JP4439392
申请日：1992-03-02
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： NARITA SUSUMU , ARAKAWA FUMIO , UCHIYAMA KUNIO , KAWASAKI IKUYA , MATSUI SHIGESUMI , HASHIMOTO KOJI
IPC分类号： G06F9/38
摘要： PURPOSE:To easily attain the program debug of the user of a microprocessor in which the simultaneously parallel and parallel execution of plural commands/ can be attained. CONSTITUTION:The operating mode of the simultaneous parallel and parallel execution is switched to the operating mode of a scalar system (the successive decode and successive execution of the plural commands) in the microprocessor. The setting of the mode is operated by setting a bit DB for a mode setting in a control register 118 in the microprocessor. The successive execution mode of the plural commands can be set in the microprocessor, so that the user can easily understand the operation of the microprocessor at the time of the debug of the program, and the debug efficiency of the program can be improved.

18. 发明专利

JPH043230A DATA PROCESSOR 失效
公开(公告)号：JPH043230A
公开(公告)日：1992-01-08
申请号：JP10470090
申请日：1990-04-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MATSUI SHIGESUMI , KAWASAKI IKUYA , KONDO YOSHIYUKI , HASHIMOTO KOJI
IPC分类号： G06F9/38 , G06F11/28
摘要： PURPOSE:To inform the internal information such as an instruction address which is being executed, etc., to the outside in the microprocessor of an instruction pre-fetch system without increasing the number of pins and providing a complicated external circuit by constituting the processor so that information for identifying an executed instruction can be outputted to the outside. CONSTITUTION:A microprocessor shows whether an instruction to be executed in the next time is on the upper side or the lower side in 32 bits by outputting a signal corresponding to the least significant bit of a program counter 15c by byte codes BC0 - BC3, by a special bus cycle. Also, since instruction buffers 10a, 10b are cleared at the time of insertion of a special bus cycle, even if the next instruction code is fetched once, it is fetched again in the next cycle. Accordingly, by looking at a signal on a data bus in the next cycle of the special bus cycle, the instruction code to be executed can also be known. In such a manner, which instruction is executed can be known easily in the outside.

19. 发明专利

JP2002163032A DATA PROCESSOR, AND DATA PROCESSING SYSTEM 失效
公开(公告)号：JP2002163032A
公开(公告)日：2002-06-07
申请号：JP2000362668
申请日：2000-11-29
申请人： HITACHI LTD
发明人： OKUBO HARUYASU , KIUCHI ATSUSHI , MATSUI SHIGESUMI
IPC分类号： G06F1/04 , G06F1/32
摘要： PROBLEM TO BE SOLVED: To satisfy both quick transition from a condition of low electric power consumption to an operation condition, and low electric power consumption. SOLUTION: This data processor 1 has a stand-by mode, a light stand-by mode and a sleep mode. Supply of a synchronization clock signal to a CPU 2 is stopped in the sleep mode, and the clock signal is supplied to other circuit modules 4-7. A multiplying and dividing operations in a clock pulse generator 3 are stopped in the stand-by mode, and supply of the synchronization signal to the CPU and other circuit modules is stopped. The multiplying and dividing operations in the clock pulse generator are allowed in the light stand-by mode, and the supply of the synchronization signal to the CPU and the other circuit modules is stopped. The transition to a command execution-allowed condition in the CPU is quick in the light stand-by mode compared with that in the stand-by mode, and electric power consumption is low therein compared with that in the sleep mode.

20. 发明专利

JP2002063149A DATA PROCESSING SYSTEM 失效
公开(公告)号：JP2002063149A
公开(公告)日：2002-02-28
申请号：JP2001156250
申请日：2001-05-25
申请人： HITACHI LTD
发明人： MATSUI SHIGESUMI , KAWASAKI IKUYA , NARITA SUSUMU , NEMOTO MASATO
IPC分类号： G06F13/12 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To provide a data processing system which is satisfactory in handleability. SOLUTION: A data processor is constituted to be connectable to a memory card or a PC card including an I/O card; a first PC card connector is constituted to be connectable to the PC card; and the external bus is divided into plural areas fixedly assigned to a ROM, a DRAM, and the PC card, and connected to the data processor, the ROM, the DRAM, and the first PC card connector. The data processor performs access to the external bus, based on a physical address in an address space. The data processor is provided with a central processing unit, which outputs an internal logical address and a memory managing unit connected to the central processing unit, which outputs the physical address to the external bus, based on the internal logical address.

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