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11. 发明专利

JPH09294075A OVERSAMPLING TYPE A/D CONVERTER 失效
公开(公告)号：JPH09294075A
公开(公告)日：1997-11-11
申请号：JP10687196
申请日：1996-04-26
申请人： HITACHI LTD
发明人： KITA MASAHITO , OKAZAKI TAKAO
IPC分类号： H03M1/12 , H03M3/02
摘要： PROBLEM TO BE SOLVED: To provide the technique to improve the S/N characteristic by preventing saturation of a signal in the oversampline type A/D converter. SOLUTION: The A/D converter is provided with a 1st amplifier means 208 having a gain of about 1/2 placed as a pre-stage circuit to a 1st integration means 202, a 2nd amplifier means 209 having a gain G1 nearly equal to that of the 1st amplifier 208 and placed between a local D/A converter means 207 and a 2nd adder means 203, and a 3rd amplifier means 210 having a gain of about 2/3 or below placed as a pre-stage circuit to a 2nd integration means 204. The saturation in the integration means is prevented by selecting the gains of the 1st amplifier means 208, the 2nd amplifier means 209 and the 3rd amplifier means as above to improve the S/N characteristic.

12. 发明专利

JPH09167929A SEMICONDUCTOR INTEGRATED CIRCUIT PROVIDED WITH OPERATONAL AMPLIFIER CIRCUIT 失效
公开(公告)号：JPH09167929A
公开(公告)日：1997-06-24
申请号：JP32882995
申请日：1995-12-18
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： OKAZAKI TAKAO , SONOBE HIROAKI
IPC分类号： H01L21/822 , H01L27/04 , H03F3/45 , H03K19/0944
摘要： PROBLEM TO BE SOLVED: To reduce the chip area of an integrated circuit provided with an inverting amplifier circuit function and a voltage follower function by using an operating mode changeover control signal so as to select a capacitor of a phase compensation circuit. SOLUTION: The capacitance of capacitors C1, C2 of a phase compensation circuit 3 is changed depending on an on/off state of a MOS transistor(TR) M16 of the circuit 3. Thus, the capacitance of the capacitors C1, C2 is selected to be optimum for the operation of the inverting amplifier circuit and for the operation of a voltage follower and an operating mode changeover control signal V2 is used to change the capacitance of the circuit 3, then the circuit 3 is in operated with an optimum phase margin at each operating mode. Then in the case of the operation of the voltage follower, the signal V2 is set to a low level and both the capacitors C1, C2 are connected nd in the case of the operation of the inverting amplifier circuit, the signal V2 is set to a high level and only the capacitor C1 is connected. Thus, the changeover between the inverting amplifier circuit function and the voltage follower function is realized and the chip area is reduced.

13. 发明专利

JPH09162654A SEMICONDUCTOR INTEGRATED CIRCUIT CONTAINING DIFFERENTIAL AMPLIFIER CIRCUIT 失效
公开(公告)号：JPH09162654A
公开(公告)日：1997-06-20
申请号：JP31533795
申请日：1995-12-04
申请人： HITACHI LTD
发明人： OKAZAKI TAKAO
IPC分类号： H03K5/08 , H03F3/45 , H03K19/0175 , H03K19/0948
摘要： PROBLEM TO BE SOLVED: To reduce the chip area of a semiconductor integrated circuit by making a differential amplifier circuit that can serve as an operational amplifier or a comparator perform the operations of both operational amplifier and comparator in time division by an operation mode switch control signal. SOLUTION: When a control signal S is set at a low level, a switch SWN supplies the bias voltage VGN to the gate of a MOS transistor TR M6. Thus the TR M6 is turned on and functions as a resistor, and this circuit operates in the functioning state of a phase compensation circuit 3. Then the circuit operates as an operational amplifier circuit when the output voltage is fed back to an inverted input terminal. When the signal S is set at a high level, the switch SWN supplies the ground potential GND to the gate of the TR M6. Thus the TR M6 is turned off to separate the circuit 3, and the circuit functions as a comparator to perform a comparison operation at a high speed.

14. 发明专利

JPH0837238A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0837238A
公开(公告)日：1996-02-06
申请号：JP19101094
申请日：1994-07-21
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： TANBA HIROKO , HASE AKIHIRO , OKAZAKI TAKAO
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/02 , H01L27/088
摘要： PURPOSE:To protect the input MOSFET's in an interface unit by placing between a plurality of power supply terminals both of unidirectional elements that are provided with so high a threshold voltage as to be turned off when power is being normally supplied. CONSTITUTION:MOSFET's Q1-Q6 with a diode connected are placed between different power supply terminals VA, VD, VX. These MOSFET's Q1-Q6 are provided with so high a threshold voltage that they will not be turned on in ordinary operating condition. This allows a thick field insulating film to be used for gate insulating films; so-called parasitic MOSFET's are used. Thus, the threshold voltage of the n-type aluminum parasitic MOSFET's Q1-Q6 is used, and potential difference between independent power supplies, which may cause the electrostatic breakdown of interface elements between the independent power supplies, is thereby canceled. This avoids the electrostatic breakdown of interface elements.

15. 发明专利

JPH03139921A ANALOG/DIGITAL HYBRID TYPE SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH03139921A
公开(公告)日：1991-06-14
申请号：JP27827389
申请日：1989-10-25
申请人： HITACHI LTD
发明人： OKAZAKI TAKAO
IPC分类号： G06J1/00 , H03M1/12
摘要： PURPOSE:To highly accurately evaluate the characteristics of an A/D conversion circuit part by supplying A/D-converted digital data obtained in each sampling period to a whole bit testing circuit in samples in accordance with a cycle synchronized with a reference clock. CONSTITUTION:A MODEM LSI 1 is provided with a digital signal processing unit 2, an analog circuit part 3 and a testing output circuit 4 and respective elements are formed on a semiconductor substrate. Since a data output cycle from an A/D conversion part 5 synchronizing with an output enable signal DOEN comes to be gradually shifted from the cycle of a reference clock signal CLK, the circuit 4 is allowed to output the converted digital data obtained in each sampling period for an analog test pattern supplied to the A/D conversion part 5 to the outside in each sampling unit in accordance with the cycle synchronizing with the reference clock signal CLK. Consequently, the evaluation of characteristics of the A/D conversion part can be highly accurately attained.

16. 发明专利

JPH0330592A LINE TERMINATING EQUIPMENT 失效
公开(公告)号：JPH0330592A
公开(公告)日：1991-02-08
申请号：JP16395489
申请日：1989-06-28
申请人： HITACHI LTD
发明人： OKAZAKI TAKAO
IPC分类号： H04L5/14 , H04L5/16 , H04L29/06 , H04Q3/42
摘要： PURPOSE:To improve the overall transmission performance of a service integrated digital network including line terminating equipment by measuring the error rate, etc., of a transmission system including the line terminating equipment in a prescribed training mode, and validating alternatively the line terminating equipment in which the best result is obtained. CONSTITUTION:Both the systems of the so-called ping-pong system and an echor cancel system are provided as a transmission system in a subscriber's line, and they are used alternatively according to the transmission characteristic of the subscriber's line. When a subscriber's line transmission system including the subscriber's line terminating equipment LTC is turned into the prescribed training mode, the subscriber's line terminating equipment LT1 or LT2 is validated alternatively so that the transmission performance such as the error rate should go to the best. Thus, the transmission system of the subscriber's line transmission system can be optimized according to the length of the line or the number of branches of the service integrated digital network including the subscriber's line terminating equipment LTC can be improved.

17. 发明专利

JPS63136717A PLL CIRCUIT 失效
公开(公告)号：JPS63136717A
公开(公告)日：1988-06-08
申请号：JP28172386
申请日：1986-11-28
申请人： HITACHI LTD
发明人： OKAZAKI TAKAO
IPC分类号： H03L7/08 , H03L7/10
摘要： PURPOSE:To decrease maximum quantity of jitter due to power voltage noise of the titled PLL circuit by providing a phase difference amplifier circuit forming a phase control signal between a phase comparator of the PLL circuit and a loop filter and a voltage controlled oscillator circuit so as to select the time width of the phase control signal to be a prescribed number of multiple of the time width of a phase difference signal. CONSTITUTION:The phase difference amplifier circuit PDA of the PLL circuit is provided with an up/down-counter circuit CTR, which decides the time width of the phase difference signal uo or do depending on the number of oscillated clock signals phi0 coming during a period while the phase difference signal is at a high level. When the phase difference signal uo or do is restored to a low level, the CTR is counted by the oscillated clock signal phi0 similarly. Then nearly the same time as the time width of the phase difference signal uo or do is counted and a phase control signal up or down is kept to a high level during that time. Thus, the time width of the phase control signal up or down is amplified/expanded to nearly twice that of the phase difference signal uo by using the phase difference amplifier circuit PDA having comparatively simple circuit constitution.

18. 发明专利

JPS62274913A VOLTAGE CONTROLLED OSCILLATING CIRCUIT 失效
公开(公告)号：JPS62274913A
公开(公告)日：1987-11-28
申请号：JP11723886
申请日：1986-05-23
申请人： HITACHI LTD
发明人： OKAZAKI TAKAO
IPC分类号： H03K3/03 , H03K3/02 , H03L7/08 , H03L7/099
摘要： PURPOSE:To perform a stable oscillating operation by providing bias circuits which raise the control voltage and the bias voltage supplied to gates of MOSFETs practically by the voltage having the same value as the threshold voltage of these MOSFETs, to suppress the variance of the oscillation frequency due to process variance. CONSTITUTION:A control voltage Vc generated by a low pass filter LPF of a PLL circuit is supplied to the gate of an N-channel MOSFET Q12. This voltage is supplied to a current mirror circuit consisting of P-channel MOSFETs Q3 and Q4 and is converted to a push-out current I2. The drain voltage of a MOSFET Q13 is supplied to the gate of a MOSFET Q15 as the output voltage of a bias circuit BC1, namely, a control voltage Vcf, and a stable control current Ic which is not affected by process variance is obtained from the drain of the MOSFET Q15. Consequently, the range where the control voltage Vc is varied to obtain a set frequency F0 of a voltage controlled oscillating circuit is narrow as shown by DELTAV', and a stable frequency characteristic is obtained.

19. 发明专利

JP2003332986A Optical module and optical communication system 有权
标题翻译：光模块和光通信系统
公开(公告)号：JP2003332986A
公开(公告)日：2003-11-21
申请号：JP2002143035
申请日：2002-05-17
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： KITA MASAHITO , ISHIBASHI MASAKAZU , FUKUCHI SATORU , OKAZAKI TAKAO , ABE YOSHITAKA
IPC分类号： H04B10/40 , H04B10/2507 , H04B10/27 , H04B10/272 , H04B10/50 , H04B10/60 , H04B10/69 , H04J14/00 , H04J14/02 , H04B10/04 , H04B10/06 , H04B10/14 , H04B10/26 , H04B10/28
摘要： PROBLEM TO BE SOLVED: To provide an optical module which inputs a burst signal and is capable of correcting a waveform distortion based on a feedforward system, and also to provide an optical communication system using the same.
SOLUTION: An optical receiver which is applied to the optical module includes a light-receiving element 1, preamplifier 2, discriminator 3, level detecting circuit 4, and duty adjusting circuit 5. When the preamplifier 2 is of a transimpedance-type, a distortion occurs in an output signal of the preamplifier 2 when receiving a signal with a large amplitude level. The waveform distortion is corrected by the circuit 5 on the basis of a monitoring result of the signal waveform of the circuit 4, so that an output signal having no waveform distortion can be obtained based on the feedforward system.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种输入突发信号并且能够基于前馈系统校正波形失真的光学模块，并且还提供使用该信号的光通信系统。解决方案：应用于光学模块的光接收器包括光接收元件1，前置放大器2，鉴别器3，电平检测电路4和占空比调节电路5.当前置放大器2是跨阻型当接收到具有大振幅电平的信号时，在前置放大器2的输出信号中发生失真。基于电路4的信号波形的监视结果，电路5校正波形失真，从而可以基于前馈系统获得没有波形失真的输出信号。版权所有（C）2004，JPO

20. 发明专利

JPH11346127A CONSTANT CURRENT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH11346127A
公开(公告)日：1999-12-14
申请号：JP15260998
申请日：1998-06-02
申请人： HITACHI LTD
发明人： OKAZAKI TAKAO
IPC分类号： G05F1/56 , H03F3/34 , H03F3/347
摘要： PROBLEM TO BE SOLVED: To reduce the noise of a constant current circuit. SOLUTION: A semiconductor substrate is formed by incorporating a reference voltage generating circuit 11, an arithmetic amplifier AMP1 for amplifying a generated reference voltage, a transistor M1 for receiving the output voltage, a resistance ladder 17 serially connected to this transistor, a switch circuit 14 for selectively feeding back the taps of the ladder 17 to the input terminal of the arithmetic amplifier, a trimming circuit 19 for controlling the operation of this switch circuit and a monitor pad 15, enabling external monitoring of a current flowing through the resistance ladder, thereby the ground level of the resistance ladder is equalized with the ground level of another circuit formed at the semiconductor substrate to attain noise reduction.

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