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11. 发明专利

JPS5974732A Cmos integrated circuit device 失效
标题翻译： CMOS集成电路设备
公开(公告)号：JPS5974732A
公开(公告)日：1984-04-27
申请号：JP18457382
申请日：1982-10-22
申请人： Hitachi Ltd
发明人： OGIUE KATSUMI , YASUI NORIMASA , TAKAHASHI OSAMU , NISHIMURA KOUTAROU , ODAKA MASANORI , MIYAOKA SHIYUUICHI
IPC分类号： G11C11/418 , G11C11/407 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/018514 , H03K19/0948
摘要： PURPOSE:To decrease the number of elements and at the same time to attain a high level of gain, by constituting an input level converting circuit with a differential MOSFET circuit and an inverter. CONSTITUTION:The input signal of an ECL level supplied from a terminal IN is applied to the gate of an n-channel MOSFETQ10. The reference voltage Vref is applied to the gate of an n-channel MOSFETQ9 of a differential type to the FETQ10. Then an n-channel MOSFETQ13 which serves as a constant current source is provided to a common source of both FETQ 9 and Q10. At the same time, p-channel MOSFET Q11 and Q12 of current mirror type are provided to the drains of FET Q9 and Q10 respectively as active loads. The output of a differential amplifying circuit is amplified again by a CMOS inverter consisting of a p-channel MOSFETQ14 and an n-channel MOSFETQ15 and then converted into a signal CMOSOUT of a CMOS level.
摘要翻译：目的：通过构成具有差分MOSFET电路和逆变器的输入电平转换电路，减少元件数量并同时获得高增益。构成：从端子IN提供的ECL电平的输入信号被施加到n沟道MOSFETQ10的栅极。参考电压Vref被施加到FETQ10的差分类型的n沟道MOSFETQ9的栅极。然后将用作恒流源的n沟道MOSFETQ13提供给FETQ 9和Q10的公共源。同时，电流镜型的p沟道MOSFET Q11和Q12分别作为有源负载提供给FET Q9和Q10的漏极。差分放大电路的输出由由p沟道MOSFETQ14和n沟道MOSFETQ15组成的CMOS反相器再次放大，然后转换为CMOS电平的信号CMOSOUT。

12. 发明专利

JPS57193066A EPROM DEVICE 失效
公开(公告)号：JPS57193066A
公开(公告)日：1982-11-27
申请号：JP5124082
申请日：1982-03-31
申请人： HITACHI LTD
发明人： FUKUDA MINORU , YAMATANI SHIGERU , NISHIMURA KOUTAROU , ENDOU AKIRA
IPC分类号： H01L27/10 , G11C16/04 , G11C16/06 , G11C17/00 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To reduce a leakage current of an EPROM device and to reduce the size of the device by composing the device of an address buffer circuit, a decoder circuit, a memory array circuit, a wiring circuit, a column switch circuit and the like. CONSTITUTION:An X-address buffer circuit ADB1, an X-decoder circuit X-DEC and memory array circuits MAR0-MAR7 are connected in series with each other, and address input terminals A5-A12 are provided at the circuit ADB1. A Y-address buffer circuit ADB2, Y-decoder circuit Y-DEC1 and column switches CS0-CS7 are similarly connected in series with each other, and input terminals A0-A4 are mounted at the circuit ADB2. Further, Y-decoder circuit Y-DEC2 and writing circuit R/W0-R/W7 are provided in series with each other, these three groups are connected to each other, and the circuit Y-DEC2 and the circuit R/W0-R/W0 are controlled by a controller CONT to which a control input signal is inputted. In this manner, the entire device is formed in IC, and a writing power terminal VPP, a power terminal VCC, and a grounded reference terminal GND are connected to the device.

13. 发明专利

JPS5651836A PELLET INSPECTING APPARATUS 失效
公开(公告)号：JPS5651836A
公开(公告)日：1981-05-09
申请号：JP12683679
申请日：1979-10-03
申请人： HITACHI LTD , HITACHI OME ELECTRONIC CO
发明人： UCHIBORI KIYOBUMI , SASAKI MASAAKI , YAMAMOTO AKIRA , YASUI NORIMASA , NISHIMURA KOUTAROU , WAKIMOTO HARUMI , NOSAKA TOSHIO
IPC分类号： H01L21/66
摘要： PURPOSE:To permit the existence of a pin-hole or foreign matter on and the surface geometry of a pellet to be automatically inspected by scanning the pellet surface with a narrow light beam and observing the variation of the reflection intensity of the light beam. CONSTITUTION:From a light source 3, a narrow light beam 5 is drawn through a collimator 4 or the like, and the whole desired surfaces of a pellet 2 are successively scanned with the beam 5 by a vibrating mirror 6 or the like. The reflected light 7 of the beam 5 is received by a light receiver 8 to observe the variation of the reflected light intensity, and a pellet 2 having a reflectance above or below a given intensity range is selected. This permits a pin-hole or foreign matter having an extremely minute diameter to be inspected as well as the inspection speed to be much higher than the eye inspection. Moreover, the inspection can be made automatic.

14. 发明专利

JPS5627952A CIRCUIT FOR GENERATING SUBSTRATE BIAS VOLTAGE 失效
公开(公告)号：JPS5627952A
公开(公告)日：1981-03-18
申请号：JP10399479
申请日：1979-08-17
申请人： HITACHI LTD
发明人： TANIMURA NOBUROU , NISHIMURA KOUTAROU , YASUI NORIMASA
IPC分类号： H01L27/04 , G05F3/20 , G11C5/14 , G11C11/34 , G11C11/4074 , G11C11/408 , G11C11/417 , H01L21/822 , H01L29/78 , H02M3/07
摘要： PURPOSE:To prevent the decrease in the operation speed and the erroneous operation of an IC circuit by eliminating the variation in a bias voltage in a semiconductor substrate due to the variation in a power supply voltage. CONSTITUTION:An oscillator ciruit 1 is constituted by a ring oscillator wherein an odd number of inverters IV1-IV5 are cascaded and the output from the final stage inverter IV5 is fedback to the first stage inverter IV1. a rectifier circuit 2 is constituted by: a capacitor C1 whcih is connected between an output line L1 and A line L2; an enhancement-mode MISFET Q1, wherein the gate and the drain are connected to the line L2 and the source is connected to the grouning point GND of the circuit; an enhancement-mode MISFET Q2, wherein the source is connected to the line L2 and the gate and the drain are connected to the line VBB; and a resistor R1 with the relatively high resistance value, which is connected between the line VBB and the grounding point GND.

15. 发明专利

JPS5467341A STATIC RAM 失效
公开(公告)号：JPS5467341A
公开(公告)日：1979-05-30
申请号：JP13341177
申请日：1977-11-09
申请人： HITACHI LTD
发明人： YASUI NORIMASA , NISHIMURA KOUTAROU
IPC分类号： G11C11/412 , G11C11/418
摘要： PURPOSE:To achieve low power consumption of RAM, by making the power consumption at chip non-selection to about zero and by reducing the power consumption at chip non-selection, static RAM of static interface type. CONSTITUTION:MISFETM1 to M6 driven with the address signal are provided, and the output deo of the inverter constituting FETM1 to M6 and charge load MISFETN7 to is fid to the memory cell 1 via the word line through the MSFETM8 M12 constituting the line drive circuit and the cell located in matrix constituting the memory cell 1. The circuit with the FF constituted with the MISFET8 to M12 of the drive circuit with this constitution is taken as the line selection decoder so that the output signal is outputted to the Word line with the address signal, and the line selection decoder input signal is inputted to the gate of the memory cell 1 delivery FETM18, M19 and M23, MU26... so that the decoder output is made to non-selection state at chip selection other than the output signal of the address buffer etc. being he input to the decoder.

16. 发明专利

JPS53142141A STATIC SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS53142141A
公开(公告)日：1978-12-11
申请号：JP5641177
申请日：1977-05-18
申请人： HITACHI LTD
发明人： YASUI NORIMASA , WAKIMOTO HARUMI , NISHIMURA KOUTAROU
IPC分类号： G11C11/41 , G11C7/24 , G11C11/413 , G11C11/417
摘要： PURPOSE:To secure a perfect prevention for the miswriting in DRM (data retantion mode) by detecting the DRM through lowering of the supply voltage.

17. 发明专利

JPS51139220A SENSE AMPLIFIER 失效
公开(公告)号：JPS51139220A
公开(公告)日：1976-12-01
申请号：JP6290075
申请日：1975-05-28
申请人： HITACHI LTD
发明人： NISHIMURA KOUTAROU
IPC分类号： G11C11/409 , G11C11/4091 , H03K3/356 , H03K5/003
摘要： PURPOSE:To increase the speed of reading through level shift obtained by separating d-c-wise the output signal from a memory cell and the input signal to a sense amplifier.

18. 发明专利

JPS60242668A MANUFACTURE OF INSULATED GATE TYPE FIELD-EFFECT SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60242668A
公开(公告)日：1985-12-02
申请号：JP22216784
申请日：1984-10-24
申请人： HITACHI LTD
发明人： YAMASHIRO OSAMU , YOU KANJI , NISHIMURA KOUTAROU , NARITA KAZUTAKA
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L21/8244 , H01L27/10 , H01L27/11
摘要： PURPOSE:To obtain a reference voltage generator, a temperature change thereof is small, by forming two IGFETs having silicon-gate electrodes having different conduction types in an silicon-monolithic semiconductor integrated circuit chip. CONSTITUTION:A thermal oxide film 102 is formed on the surface of a semiconductor substrate 101, and a gate oxide film (SiO2) 103 is shaped to the surface of the semiconductor substrate exposed through etching. Silicon is deposited on the whole main surface, and a polycrystalline silicon layer is formed and etched selectively. A CVD-SiO2 film 105 is deposited, and left only on a high resistance section such as a memory cell load resistor and the polycrystalline silicon layer in an intrinsic level gate section 104a. Phosphorus is diffused into the semiconductor substrate 101 while using the polycrystalline silicon layer as a mask to shape source regions and drain regions 106. An impurity is also introduced into the polycrystalline silicon layer at that time, and gate electrodes 104b, a direct contact 104c and a polycrystalline silicon wiring section 104d are formed.

19. 发明专利

JPS60143011A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS60143011A
公开(公告)日：1985-07-29
申请号：JP22217084
申请日：1984-10-24
申请人： HITACHI LTD
发明人： YAMASHIRO OSAMU , YOU KANJI , NISHIMURA KOUTAROU , NARITA KAZUTAKA
IPC分类号： H03F3/343 , H01L21/822 , H01L27/04 , H01L29/78 , H03F3/34 , H03F3/347
摘要： PURPOSE:To obtain a reference voltage generator with less temperature change by setting a logical threshold value of a semiconductor integrated circuit based on the difference between the 1st and 2nd threshold voltages different from each other. CONSTITUTION:An IGFETT1 having a threshold voltage Vth1 and an IGFETT2 having a threshold voltage Vth2 are connected in series in a form of MOS diode. In setting resistors R1, R2 to a sufficiently large value in comparison with the impedance of the T1, T2 respectively, since the difference between the gate voltage of the T1 and an output voltage V2 is expressed as V1-V2 Vth1 and V1 Vth2, the reference V2 Vth1-Vth2 is obtained and the logical threshold voltage is set to the difference of the threshold voltages of the T1 and T2. Since the threshold voltage is controlled at manufactured based on the energy gap specific to the semiconductor, a reference voltage generator with less temprature dependancy and less variance between manufacture lots is obtained.

20. 发明专利

JPS59188883A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：JPS59188883A
公开(公告)日：1984-10-26
申请号：JP6218483
申请日：1983-04-11
申请人： Hitachi Ltd
发明人： YASUI NORIMASA , NISHIMURA KOUTAROU , TANIMURA NOBUROU
IPC分类号： G11C11/413 , G06F1/26 , G11C11/34
CPC分类号： G11C11/34
摘要： PURPOSE:To exclude an external circuit which backs up a memory to decrease the number of component parts and to facilitate easy assembly as well as to reduce the packaging area, by always driving a memory element part with a battery power supply. CONSTITUTION:The writing current is supplied to each data line D in a memory array 11 of a static RAM consisting of a flip-flop type memory cell via MOSFETs Q1 and Q1 serving as load resistnaces by means of a power supply line L. This line L is connected to the 1st power supply terminal 21 together with the power supply line of a peripheral circuit of a control circuit 16, etc. The power supply lines l1, l2- which supply the data holding current to a memory cell of each row in the array 11 are connected to the 2nd power supply terminal 22 to supply the power supply voltage VCC2 from a power supply of 3-5V. This eliminate the need for a back-up external circuit consisting of a power supply voltage drop detecting circuit, a power supply changeover switch circuit, etc.
摘要翻译：目的：为了排除备份存储器的外部电路，以减少组件数量，并且通过总是用电池电源驱动存储元件部件，便于组装以及减少封装区域。构成：通过供电线L作为负载阻抗的MOSFET Q1和Q1，将写入电流提供给由触发型存储单元构成的静态RAM的存储器阵列11中的每个数据线D.该行 L与控制电路16的外围电路的电源线一起连接到第一电源端子21等。将数据保持电流提供给每行的存储单元的电源线路111，112 阵列11连接到第二电源端子22，以从3-5V的电源供给电源电压VCC2。这不需要由电源电压降检测电路，电源切换开关电路等组成的备用外部电路。

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