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11. 发明授权

US06281143B1 Method of forming borderless contact 失效
标题翻译：形成无边界接触的方法
公开(公告)号：US06281143B1
公开(公告)日：2001-08-28
申请号：US09334864
申请日：1999-06-17
申请人： Michael W C Huang , Hsueh-Hao Shih , Gwo-Shii Yang , Tri-Rung Yew
发明人： Michael W C Huang , Hsueh-Hao Shih , Gwo-Shii Yang , Tri-Rung Yew
IPC分类号： H01L2131
CPC分类号： H01L21/76897 , H01L21/28518 , H01L21/3143 , H01L21/321
摘要： A method for forming borderless contact is disclosed. The method includes providing a substrate with active areas and a trench isolation region in which the active areas are silcide. Then, the substrate is nitridized such that a titanium nitride layer is formed on the active areas and a silicon oxynitride is formed on the trench isolation region. A dielectric layer is deposited on the substrate and an opening is etched in the dielectric layer in which the opening overlies both a portion of the trench isolation region and a portion of the active area.
摘要翻译：公开了一种形成无边界接触的方法。该方法包括提供具有有源区的衬底和沟槽隔离区，其中有源区是硅化物。然后，将衬底氮化，使得在有源区上形成氮化钛层，并在沟槽隔离区上形成氮氧化硅。介电层沉积在衬底上，并且在电介质层中蚀刻开口，其中开口覆盖沟槽隔离区的一部分和有源区的一部分。

12. 发明授权

US6146974A Method of fabricating shallow trench isolation (STI) 有权
标题翻译：浅沟槽隔离（STI）制造方法
公开(公告)号：US6146974A
公开(公告)日：2000-11-14
申请号：US348884
申请日：1999-07-01
申请人： Chih-Chien Liu , Cheng-Yuan Tsai , Gwo-Shii Yang , Juan-Yuan Wu
发明人： Chih-Chien Liu , Cheng-Yuan Tsai , Gwo-Shii Yang , Juan-Yuan Wu
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A method of fabricating shallow trench isolation (STI) forms a trench in a substrate and a liner oxide layer in the trench. A first high density plasma chemical vapor deposition (HDPCVD) is performed to form a conformal oxide layer on the liner oxide layer, without applying bias to the substrate. A second HDPCVD is then performed to form an oxide layer that fills the trench and covers the conformal oxide layer on the conformal oxide layer.
摘要翻译：制造浅沟槽隔离（STI）的方法在衬底中形成沟槽，并在沟槽中形成衬垫氧化物层。执行第一高密度等离子体化学气相沉积（HDPCVD）以在衬垫氧化物层上形成保形氧化物层，而不对衬底施加偏压。然后执行第二HDPCVD以形成填充沟槽并覆盖保形氧化物层上的共形氧化物层的氧化物层。

13. 发明申请

US20100084683A1 LIGHT EMITTING DIODE PACKAGE AND FABRICATING METHOD THEREOF 审中-公开
标题翻译：发光二极管封装及其制造方法
公开(公告)号：US20100084683A1
公开(公告)日：2010-04-08
申请号：US12632737
申请日：2009-12-07
申请人： Kou-Rueh Lai , Gwo-Shii Yang , Kung-Chi Ho , Hu-Chen Tsai , Wen-Chuan Wang
发明人： Kou-Rueh Lai , Gwo-Shii Yang , Kung-Chi Ho , Hu-Chen Tsai , Wen-Chuan Wang
IPC分类号： H01L33/00 , H01L21/50
CPC分类号： H01L25/167 , H01L2224/04042 , H01L2224/16245 , H01L2224/48091 , H01L2224/48247 , H01L2224/49107 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： A light emitting diode (LED) package is provided. The LED package includes a carrier, a package housing, a strength enhancement structure, an ESD protector and an LED chip. The carrier has a first surface and a second surface. The carrier includes a first electrode and a second electrode, wherein a gap is between the first electrode and the second electrode. The package housing is disposed on the carrier and has a first aperture and a second aperture. The first surface is exposed by the first aperture while the second surface is exposed by the second aperture. The strength enhancement structure is disposed at the gap. The ESD protector is disposed on the carrier and located within the second aperture. The LED chip is disposed on the carrier and located within the first aperture, wherein the ESD protector and the LED chip is electrically connected to the carrier.
摘要翻译：提供了一种发光二极管（LED）封装。 LED封装包括载体，封装外壳，强度增强结构，ESD保护器和LED芯片。载体具有第一表面和第二表面。载体包括第一电极和第二电极，其中间隙在第一电极和第二电极之间。包装壳体设置在载体上并具有第一孔和第二孔。第一表面由第一孔暴露，而第二表面被第二孔露出。强度增强结构设置在间隙处。 ESD保护器设置在载体上并且位于第二孔内。 LED芯片设置在载体上并且位于第一孔内，其中ESD保护器和LED芯片电连接到载体。

14. 发明授权

US06583489B2 Method for forming interconnect structure with low dielectric constant 有权
公开(公告)号：US06583489B2
公开(公告)日：2003-06-24
申请号：US10103835
申请日：2002-03-25
申请人： Sung-Hsiung Wang , Yi-Min Huang , Gwo-Shii Yang , Chiung-Sheng Hsiung , Hsueh-Chung Chen , Chih-Chien Liu
发明人： Sung-Hsiung Wang , Yi-Min Huang , Gwo-Shii Yang , Chiung-Sheng Hsiung , Hsueh-Chung Chen , Chih-Chien Liu
IPC分类号： H01L2900
CPC分类号： H01L21/76802 , H01L21/31612 , H01L21/31625 , H01L21/31629 , H01L21/318 , H01L21/76837 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , Y10T428/24917 , Y10T428/24926 , H01L2924/00
摘要： The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.

15. 发明授权

US06218243B1 Method of fabricating a DRAM capacitor 有权
标题翻译：制造DRAM电容器的方法
公开(公告)号：US06218243B1
公开(公告)日：2001-04-17
申请号：US09252127
申请日：1999-02-18
申请人： Wayne Tan , Kun-Chi Lin , Gwo-Shii Yang
发明人： Wayne Tan , Kun-Chi Lin , Gwo-Shii Yang
IPC分类号： H01L218242
CPC分类号： H01L28/84 , H01L27/10852
摘要： A method of fabricating a DRAM capacitor includes the step of forming an insulated layer and an etching stop layer successively on a substrate having a device structure. A contact window is formed within the etching stop layer and the insulated layer. A conductive layer is formed on the etching layer to fill in the contact window and patterned to serve as a lower electrode of the capacitor. A highly doped dielectric layer is then formed on the lower electrode and a thermal process is performed to diffuse the dopants inside the highly doped dielectric layer into the surface of the lower electrode. The dielectric layer is removed. A capacitor dielectric layer and an upper electrode are successively formed on the lower electrode to complete the fabrication of the capacitor.
摘要翻译：制造DRAM电容器的方法包括在具有器件结构的衬底上依次形成绝缘层和蚀刻停止层的步骤。在蚀刻停止层和绝缘层内形成接触窗。在蚀刻层上形成导电层以填充接触窗口并图案化以用作电容器的下电极。然后在下电极上形成高掺杂的电介质层，并进行热处理，以将高掺杂电介质层内的掺杂剂扩散到下电极的表面。去除电介质层。电容器电介质层和上电极依次形成在下电极上以完成电容器的制造。

16. 发明申请

US20070194422A1 LIGHT EMITTING DIODE PACKAGE AND FABRICATING METHOD THEREOF 审中-公开
标题翻译：发光二极管封装及其制造方法
公开(公告)号：US20070194422A1
公开(公告)日：2007-08-23
申请号：US11535991
申请日：2006-09-28
申请人： Kou-Rueh Lai , Gwo-Shii Yang , Kung-Chi Ho , Hu-Chen Tsai , Wen-Chuan Wang
发明人： Kou-Rueh Lai , Gwo-Shii Yang , Kung-Chi Ho , Hu-Chen Tsai , Wen-Chuan Wang
IPC分类号： H01L23/06
CPC分类号： H01L25/167 , H01L2224/48227 , H01L2224/48247 , H01L2224/49107 , H01L2224/48091 , H01L2924/00014
摘要： A Light Emitting Diode (LED) package including a carrier, a package housing, an LED chip, and an electrostatic discharge protector (ESD protector) is provided. The package housing encapsulates a part of the carrier so as to provide a chip-accommodating space on the carrier. The LED chip disposed on the carrier and located in the chip-accommodating space is electrically connected to the carrier. The ESD protector disposed on the carrier and encapsulated by the package housing is electrically connected to the carrier. The LED package has excellent light-emitting intensity, since the light emitted from the LED chip is not absorbed by the ESD protector encapsulated by the package housing. Additionally, a fabricating method of the LED package is also provided.
摘要翻译：提供了包括载体，封装壳体，LED芯片和静电放电保护器（ESD保护器）的发光二极管（LED）封装。封装壳体封装载体的一部分，以便在载体上提供芯片容纳空间。设置在载体上并且位于芯片容纳空间中的LED芯片电连接到载体。设置在载体上并被封装壳体封装的ESD保护器电连接到载体。 LED封装具有优异的发光强度，因为从LED芯片发出的光不被由封装壳体封装的ESD保护器吸收。此外，还提供了LED封装的制造方法。

17. 发明授权

US06249138B1 Method for testing leakage current caused self-aligned silicide 有权
标题翻译：泄漏电流测试方法引起自对准硅化物
公开(公告)号：US06249138B1
公开(公告)日：2001-06-19
申请号：US09447846
申请日：1999-11-23
申请人： Michael WC Huang , Gwo-Shii Yang , Hsiao-Ling Lu , Wen-Yi Hsieh
发明人： Michael WC Huang , Gwo-Shii Yang , Hsiao-Ling Lu , Wen-Yi Hsieh
IPC分类号： G01R3126
CPC分类号： G01R31/2648
摘要： A method of testing a leakage current caused by a self-aligned silicide process is described. The invention uses different test structure to monitor degree of and reason for a leakage current caused by a self-aligned silicide process. While monitoring a self-aligned silicide process performed on a metal-oxide semiconductor transistor without a LDD region, in addition to considering a leakage current occurring from the metal silicide layer to the junction and occurring at edge of the metal silicide layer, the invention further considers a leakage current at comer of the metal silicide layer. For a metal-oxide semiconductor transistor having a LDD region, the invention further considers a leakage current from the metal silicide layer to the LDD region. The invention monitors a leakage current at comer of the metal silicide layer.
摘要翻译：描述了由自对准硅化物工艺引起的漏电流的测试方法。本发明使用不同的测试结构来监测由自对准硅化物工艺引起的漏电流的程度和原因。在监视对没有LDD区域的金属氧化物半导体晶体管进行的自对准硅化物处理的同时，除了考虑从金属硅化物层发生到结以及在金属硅化物层的边缘处发生的漏电流之外，本发明进一步考虑在金属硅化物层的角落处的漏电流。对于具有LDD区域的金属氧化物半导体晶体管，本发明还考虑了从金属硅化物层到LDD区域的漏电流。本发明监测金属硅化物层的角落处的漏电流。

18. 发明授权

US06200904B1 Method of forming a contact hole of a DRAM 有权
标题翻译：形成DRAM接触孔的方法
公开(公告)号：US06200904B1
公开(公告)日：2001-03-13
申请号：US09323546
申请日：1999-06-01
申请人： Wayne Tan , Gwo-Shii Yang , Kun-Chi Lin
发明人： Wayne Tan , Gwo-Shii Yang , Kun-Chi Lin
IPC分类号： H01L21302
CPC分类号： H01L21/76831 , H01L21/76804 , H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10885
摘要： The present invention relates to a method of forming a contact hole of a DRAM on the semiconductor wafer. The semiconductor wafer comprises a substrate, a first dielectric layer, two bit lines on the first dielectric layer, a second dielectric layer, and a photo-resist layer comprising an opening to define the pattern of the contact hole. The method comprises performing a first anisotropic etching process to vertically remove a portion of the two dielectric layers and two bit lines to grossly form the contact hole, removing the photo-resist layer in its entirety, performing a thermal oxidation to form a silicon oxide layer on the side walls of the two bit lines, then forming a silicon nitride layer on the surface of the contact hole, and performing a dry etching to remove the silicon nitride layer. There is a silicon oxide layer and a silicon nitride layer between the bit line and the contact hole, and the contact area of the contact hole will not be reduced.
摘要翻译：本发明涉及在半导体晶片上形成DRAM的接触孔的方法。半导体晶片包括基板，第一介电层，第一电介质层上的两个位线，第二电介质层和包含用于限定接触孔的图案的开口的光致抗蚀剂层。该方法包括执行第一各向异性蚀刻工艺以垂直去除两个电介质层和两个位线的一部分，以大致形成接触孔，完全去除光致抗蚀剂层，进行热氧化以形成氧化硅层在两个位线的侧壁上，然后在接触孔的表面上形成氮化硅层，并进行干蚀刻以除去氮化硅层。位线和接触孔之间有一个氧化硅层和一个氮化硅层，接触孔的接触面积不会减小。

19. 发明授权

US06806182B2 Method for eliminating via resistance shift in organic ILD 失效
标题翻译：消除有机ILD中电阻移位的方法
公开(公告)号：US06806182B2
公开(公告)日：2004-10-19
申请号：US10137274
申请日：2002-05-01
申请人： Darryl Restaino , Shahab Siddiqui , Erdem Kaltalioglu , Delores Bennett , Chih-Chih Liu , Hsueh-Chung Chen , Tong-Yu Chen , Gwo-Shii Yang , Chiung-Sheng Hsiung
发明人： Darryl Restaino , Shahab Siddiqui , Erdem Kaltalioglu , Delores Bennett , Chih-Chih Liu , Hsueh-Chung Chen , Tong-Yu Chen , Gwo-Shii Yang , Chiung-Sheng Hsiung
IPC分类号： H01L214763
CPC分类号： H01L21/02252 , H01L21/02118 , H01L21/02164 , H01L21/022 , H01L21/02203 , H01L21/02304 , H01L21/02323 , H01L21/0234 , H01L21/3121 , H01L21/31695 , H01L21/76826 , H01L21/76832 , H01L21/76834
摘要： Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.
摘要翻译：在覆盖有机层间介质之前，将粘合促进剂施加到覆盖层和粘附促进剂的氧化之后，减少了体现多层金属和有机层间电介质的半导体晶片的热循环过程中的电阻问题。

20. 发明授权

US06750129B2 Process for forming fusible links 有权
标题翻译：形成易熔连接的工艺
公开(公告)号：US06750129B2
公开(公告)日：2004-06-15
申请号：US10292399
申请日：2002-11-12
申请人： Gwo-Shii Yang , Jen Kon Chen , Hsueh-Chung Chen , Hans-Joachim Barth , Chiung-Sheng Hsiung , Chih-Chien Liu , Tong-Yu Chen , Yi-hsiung Lin , Chih-Chao Yang
发明人： Gwo-Shii Yang , Jen Kon Chen , Hsueh-Chung Chen , Hans-Joachim Barth , Chiung-Sheng Hsiung , Chih-Chien Liu , Tong-Yu Chen , Yi-hsiung Lin , Chih-Chao Yang
IPC分类号： H01L213205
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding pads. The process can be applied in the fabrication of integrated circuits that employ copper metallization and low k dielectric materials. After patterning the final metal (aluminum) layer to form the fusible links and the bonding pads, a dielectric etch stop layer is formed over the final metal layer before a passivation layer is deposited. The passivation layer is removed in areas over the fusible links and the bonding pads. The dielectric etch stop layer is removed either from above the bonding pads only, or from above both the bonding pads and the fusible links.
摘要翻译：一种用于在集成电路中形成可熔链节的方法，其中可熔链在最终金属化层中与焊盘同时形成。该方法可以应用于采用铜金属化和低k电介质材料的集成电路的制造中。在对最终的金属（铝）层进行构图以形成可熔连接件和接合焊盘之后，在沉积钝化层之前，在最终的金属层上形成介电蚀刻停止层。钝化层在可熔接头和接合焊盘上的区域中被去除。电介质蚀刻停止层仅从接合焊盘上方或者从焊盘和可熔连接部上方移除。

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