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11. 发明申请

US20130054901A1 PROPORTIONAL MEMORY OPERATION THROTTLING 有权
标题翻译：比例存储器操作曲线
公开(公告)号：US20130054901A1
公开(公告)日：2013-02-28
申请号：US13217513
申请日：2011-08-25
申请人： Sukalpa Biswas , Hao Chen
发明人： Sukalpa Biswas , Hao Chen
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A memory controller receives memory operations via an interface which may include multiple ports. Each port is coupled to real-time or non-real-time requestors, and the received memory operations are classified as real-time or non-real-time and stored in queues prior to accessing memory. Within the memory controller, pending memory operations from the queues are scheduled for servicing. Logic throttles the scheduling of non-real-time memory operations in response to detecting a number of outstanding memory operations has exceeded a threshold. The throttling is proportional to the number of outstanding memory operations.
摘要翻译：存储器控制器经由可以包括多个端口的接口来接收存储器操作。每个端口耦合到实时或非实时请求者，并且所接收的存储器操作被分类为实时或非实时的，并且在访问存储器之前存储在队列中。在内存控制器中，排队等待的内存操作计划进行维修。响应于检测到未完成的存储器操作的数量已经超过阈值，逻辑控制非实时存储器操作的调度。节流与未完成记忆操作的数量成比例。

12. 发明申请

US20120072677A1 Multi-Ported Memory Controller with Ports Associated with Traffic Classes 审中-公开
标题翻译：具有与流量类相关的端口的多端口存储器控制器
公开(公告)号：US20120072677A1
公开(公告)日：2012-03-22
申请号：US12883848
申请日：2010-09-16
申请人： Sukalpa Biswas , Hao Chen
发明人： Sukalpa Biswas , Hao Chen
IPC分类号： G06F12/00
CPC分类号： G06F13/18
摘要： In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.
摘要翻译：在一个实施例中，存储器控制器包括多个端口。每个端口可能专用于不同类型的流量。在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。存储器控制器可以被配置为基于QoS参数在不同端口上接收的调度操作。在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。

13. 发明申请

US20080307286A1 Combined Single Error Correction/Device Kill Detection Code 有权
标题翻译：组合单错误纠正/设备杀毒检测码
公开(公告)号：US20080307286A1
公开(公告)日：2008-12-11
申请号：US11758322
申请日：2007-06-05
申请人： Brian P. Lilly , Robert Gries , Sridhar P. Subramanian , Sukalpa Biswas , Hao Chen
发明人： Brian P. Lilly , Robert Gries , Sridhar P. Subramanian , Sukalpa Biswas , Hao Chen
IPC分类号： H03M13/00
CPC分类号： H03M13/09 , G06F11/1004
摘要： In one embodiment, an apparatus comprises a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission comprising M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.
摘要翻译：在一个实施例中，一种装置包括耦合到控制电路的检查/校正电路。检查/校正电路被耦合以接收数据块和相应的校验位。数据块作为N个传输被接收，每个传输包括M个数据位和L个校验位。检查/校正电路被配置为响应于M个数据位和L个校验位来检测M个数据位中K位的多个非重叠窗口中的每一个中的一个或多个错误。控制电路被配置为记录多个窗口中哪一个具有检测到的错误，并且如果多个窗口的给定窗口在块的N个传输中的每一个中都检测到错误，则控制电路被配置为发信号设备故障 K，L，M和N中的每一个是大于1的整数。

14. 发明授权

US09043570B2 System cache with quota-based control 有权
标题翻译：具有基于配额控制的系统缓存
公开(公告)号：US09043570B2
公开(公告)日：2015-05-26
申请号：US13610642
申请日：2012-09-11
申请人： Sukalpa Biswas , Shinye Shiu , James Wang
发明人： Sukalpa Biswas , Shinye Shiu , James Wang
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/08 , G06F12/0831 , G06F12/0871 , G06F12/123 , G06F12/126 , G06F2212/6042 , Y02D10/13
摘要： Methods and apparatuses for implementing a system cache with quota-based control. Quotas may be assigned on a group ID basis to each group ID that is assigned to use the system cache. The quota does not reserve space in the system cache, but rather the quota may be used within any way within the system cache. The quota may prevent a given group ID from consuming more than a desired amount of the system cache. Once a group ID's quota has been reached, no additional allocation will be permitted for that group ID. The total amount of allocated quota for all group IDs can exceed the size of system cache, such that the system cache can be oversubscribed. The sticky state can be used to prioritize data retention within the system cache when oversubscription is being used.
摘要翻译：实现基于配额控制的系统缓存的方法和装置。可以根据分配给使用系统高速缓存的每个组ID将组ID分配给配额。配额不会在系统缓存中保留空间，而是可以以任何方式在系统缓存中使用配额。配额可能会阻止给定组ID消耗超过所需数量的系统高速缓存。达到组ID的配额后，不会对该组ID进行额外的分配。所有组ID的分配配额的总量可能超过系统缓存的大小，从而可以超额订阅系统缓存。当使用超额认购时，粘性状态可用于优先考虑系统缓存内的数据保留。

15. 发明申请

US20140059297A1 SYSTEM CACHE WITH STICKY ALLOCATION 有权
标题翻译：系统缓存与粘贴分配
公开(公告)号：US20140059297A1
公开(公告)日：2014-02-27
申请号：US13594932
申请日：2012-08-27
申请人： Sukalpa Biswas , Shinye Shiu , James Wang
发明人： Sukalpa Biswas , Shinye Shiu , James Wang
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , Y02D10/13
摘要： Methods and apparatuses for implementing a system cache within a memory controller. Multiple requesting agents may allocate cache lines in the system cache, and each line allocated in the system cache may be associated with a specific group ID. Also, each line may have a corresponding sticky state which indicates if the line should be retained in the cache. The sticky state is determined by an allocation hint provided by the requesting agent. When a cache line is allocated with the sticky state, the line will not be replaced by other cache lines fetched by any other group IDs.
摘要翻译：用于在存储器控制器内实现系统高速缓存的方法和装置。多个请求代理可以在系统高速缓存中分配高速缓存行，并且在系统高速缓存中分配的每一行可以与特定组ID相关联。此外，每行可以具有相应的粘性状态，其指示该行是否应保留在高速缓存中。粘性状态由请求代理提供的分配提示确定。当缓存行被分配为粘性状态时，该行不会被任何其他组ID获取的其他高速缓存行所替代。

16. 发明授权

US08631213B2 Dynamic QoS upgrading 有权
标题翻译：动态QoS升级
公开(公告)号：US08631213B2
公开(公告)日：2014-01-14
申请号：US12883878
申请日：2010-09-16
申请人： Sukalpa Biswas , Hao Chen , Ruchi Wadhawan
发明人： Sukalpa Biswas , Hao Chen , Ruchi Wadhawan
IPC分类号： G06F12/00
CPC分类号： G06F13/1694 , G06F13/1684
摘要： In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.
摘要翻译：在一个实施例中，存储器控制器包括多个端口。每个端口可能专用于不同类型的流量。在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。存储器控制器可以被配置为基于QoS参数调度在不同端口上接收的操作。在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。

17. 发明授权

US08458406B2 Multiple critical word bypassing in a memory controller 有权
标题翻译：多个关键字在内存控制器中绕过
公开(公告)号：US08458406B2
公开(公告)日：2013-06-04
申请号：US12955699
申请日：2010-11-29
申请人： Sukalpa Biswas , Hao Chen , Brian P. Lilly
发明人： Sukalpa Biswas , Hao Chen , Brian P. Lilly
IPC分类号： G06F2/00
CPC分类号： G06F12/0893 , G06F13/1673
摘要： In one embodiment, a memory controller may be configured to transmit two or more critical words (or beats) corresponding to two or more different read requests prior to returning the remaining beats of the read requests. Such an embodiment may reduce latency to the sources of the memory requests, which may be stalled awaiting the critical words. The remaining words may fill a cache block or other buffer, but may not be required by the sources as quickly as the critical words in order to support higher performance. In some embodiments, once a remaining beat of a block is transmitted, all of the remaining beats may be transmitted contiguously. In other embodiments, additional critical words may be forwarded between remaining beats of a block.
摘要翻译：在一个实施例中，存储器控制器可以被配置为在返回读取请求的剩余节拍之前发送对应于两个或更多个不同读取请求的两个或更多个关键词（或节拍）。这样的实施例可以减少对可能被停止等待关键词的存储器请求的来源的等待时间。剩余的单词可以填充缓存块或其他缓冲区，但可能不需要来源与关键字一样快以支持更高的性能。在一些实施例中，一旦发送了块的剩余节拍，则所有剩余的节拍可以连续传输。在其他实施例中，可以在块的剩余节拍之间转发附加关键词。

18. 发明申请

US20130054902A1 ACCELERATING BLOCKING MEMORY OPERATIONS 有权
标题翻译：加速阻塞存储器操作
公开(公告)号：US20130054902A1
公开(公告)日：2013-02-28
申请号：US13221461
申请日：2011-08-30
申请人： Sukalpa Biswas , Hao Chen
发明人： Sukalpa Biswas , Hao Chen
IPC分类号： G06F12/00
CPC分类号： G06F13/1668
摘要： A memory controller, system, and method for accelerating blocking memory operations. A memory controller reorders memory operations so as to maximize efficient use of the memory device bus. When data for a newer memory operation is retrieved from memory and ready to be returned to a source device, the newer memory operation can be held up waiting for an older memory operation to be completed. In response, the memory controller forwards a push request for the older memory operation to a memory channel unit. The memory channel unit then sets a push bit of the older memory operation, which expedites the scheduling of the older memory operation.
摘要翻译：一种用于加速阻塞存储器操作的存储器控制器，系统和方法。存储器控制器重新排列存储器操作，以便最大限度地有效地使用存储器设备总线。当从存储器检索到较新的存储器操作的数据并准备返回到源设备时，可以停止较新的存储器操作等待较旧的存储器操作完成。作为响应，存储器控制器将用于较旧存储器操作的推送请求转发到存储器通道单元。然后，存储器通道单元设置较旧存储器操作的推送位，这加快了较旧存储器操作的调度。

19. 发明申请

US20120072678A1 Dynamic QoS upgrading 有权
标题翻译：动态QoS升级
公开(公告)号：US20120072678A1
公开(公告)日：2012-03-22
申请号：US12883878
申请日：2010-09-16
申请人： Sukalpa Biswas , Hao Chen , Ruchi Wadhawan
发明人： Sukalpa Biswas , Hao Chen , Ruchi Wadhawan
IPC分类号： G06F12/00
CPC分类号： G06F13/1694 , G06F13/1684
摘要： In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.
摘要翻译：在一个实施例中，存储器控制器包括多个端口。每个端口可能专用于不同类型的流量。在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。存储器控制器可以被配置为基于QoS参数在不同端口上接收的调度操作。在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。

20. 发明申请

US20120046930A1 Controller and Fabric Performance Testing 失效
标题翻译：控制器和织物性能测试
公开(公告)号：US20120046930A1
公开(公告)日：2012-02-23
申请号：US12860668
申请日：2010-08-20
申请人： Marc A. Schaub , Shun Wai Go , Sukalpa Biswas , Timothy J. Millet
发明人： Marc A. Schaub , Shun Wai Go , Sukalpa Biswas , Timothy J. Millet
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： In an embodiment, a model may be created using a register-transfer level (RTL) representation (or other cycle-accurate representation) of the controller and the circuitry in the communication fabric to the controller. The request sources may be replaced by transactors, which may generate transactions to test the performance of the fabric and controller. Accordingly, only the designs of the controller and the fabric circuitry may be needed to model performance in this embodiment. In an embodiment, at least some of the transactors may be behavioral transactors that attempt to mimic the operation of corresponding request sources. Other transactors may be statistical distributions, in some embodiments. In an embodiment, the transactors may include a transaction generator (e.g. behavioral or statistical) and a protocol translator configured to convert generated transactions to the communication protocol in use at the point that the transactor is connected to the fabric.
摘要翻译：在一个实施例中，可以使用控制器的寄存器传送级（RTL）表示（或其他周期精确表示）以及到控制器的通信结构中的电路来创建模型。请求源可以被交易者代替，交易者可以生成事务来测试结构和控制器的性能。因此，在该实施例中，仅需要控制器和结构电路的设计来建模性能。在一个实施例中，至少一些事务者可以是尝试模拟相应请求源的操作的行为事务者。在一些实施例中，其他交易者可以是统计分布。在一个实施例中，事务处理器可以包括交易发生器（例如行为或统计）和协议转换器，其被配置为在交易者连接到该结构的点处将生成的交易转换为使用中的通信协议。

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