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11. 发明授权

US06487134B2 Single-event upset tolerant latch for sense amplifiers 有权
标题翻译：用于读出放大器的单事件不耐受锁存器
公开(公告)号：US06487134B2
公开(公告)日：2002-11-26
申请号：US09927059
申请日：2001-08-09
申请人： Nandor G. Thoma , Scott E. Doyle
发明人： Nandor G. Thoma , Scott E. Doyle
IPC分类号： G11C700
CPC分类号： G11C7/06
摘要： A single-event upset tolerant sense latch circuit for sense amplifiers is disclosed. The single-event upset tolerant sense latch circuit includes a first set of isolation transistors, a second set of isolation transistors, a first set of dual-path inverters, a second set of dual-path inverters, and an isolation transistor. The first set of isolation transistors is coupled to a first bitline, and the second set of isolation transistors is coupled to a second bitline. The second bitline is complementary to the first bitline. The first set of dual-path inverters is coupled to the first set of isolation transistors, and the first set of dual-path inverters includes a first transistor connected to a second transistor in series along with a third transistor connected to a fourth transistor in series. The second set of dual-path inverters is coupled to the second set of isolation transistors, and the second set of dual-path inverters includes a fifth transistor connected to a sixth transistor in series along with a seventh transistor connected to an eighth transistor in series. The isolation transistor couples the first and second sets of dual-path inverters to ground.
摘要翻译：公开了一种用于读出放大器的单事件容错读出锁存电路。单事件歪曲容忍检测锁存电路包括第一组隔离晶体管，第二组隔离晶体管，第一组双通道反相器，第二组双通道反相器和隔离晶体管。第一组隔离晶体管耦合到第一位线，第二组隔离晶体管耦合到第二位线。第二个位线是第一个位线的补充。第一组双通道逆变器耦合到第一组隔离晶体管，并且第一组双通道反相器包括连接到与串联连接到第四晶体管的第三晶体管串联的第二晶体管的第一晶体管。第二组双通道逆变器耦合到第二组隔离晶体管，第二组双通道反相器包括连接到与串联连接到第八晶体管的第七晶体管串联连接的第六晶体管的第五晶体管。隔离晶体管将第一组和第二组双通道逆变器耦合到地。

12. 发明授权

US5525914A CMOS driver circuit 失效
标题翻译： CMOS驱动电路
公开(公告)号：US5525914A
公开(公告)日：1996-06-11
申请号：US376704
申请日：1995-01-23
申请人： Tai Cao , Satyajit Dutta , Thai Q. Nguyen , Nandor G. Thoma , Thanh D. Trinh
发明人： Tai Cao , Satyajit Dutta , Thai Q. Nguyen , Nandor G. Thoma , Thanh D. Trinh
IPC分类号： H03K3/356 , H03K19/0185
CPC分类号： H03K3/35613 , H03K3/356034
摘要： A clock distribution system for a data processing system is implemented in CMOS technology wherein a full-swing differential clock signal is converted to a low-voltage swing differential clock signal by a driver's circuit and then returned to a full-swing differential clock signal at each receiver circuit.
摘要翻译：用于数据处理系统的时钟分配系统在CMOS技术中实现，其中全摆幅差分时钟信号由驱动器电路转换为低电压摆幅差分时钟信号，然后在每个时钟信号返回到全频差分时钟信号接收电路。

13. 发明授权

US5442776A Electronically tuneable computer clocking system and method of electronically tuning distribution lines of a computer clocking system 失效
标题翻译：电子调谐计算机时钟系统和电子调谐计算机时钟系统配线的方法
公开(公告)号：US5442776A
公开(公告)日：1995-08-15
申请号：US269226
申请日：1994-06-30
申请人： Robert P. Masleid , Nandor G. Thoma
发明人： Robert P. Masleid , Nandor G. Thoma
IPC分类号： G06F1/10 , H03K5/00 , H03K5/13 , H03K5/15 , G06F15/20 , H03J1/00
CPC分类号： H03K5/1504
摘要： A resonant clocking system is described which utilizes a feedback clock signal from the master clock node on a clocked chip and wherein the feedback clock signal is detected with a phase detector to determine the relevant phasing of the transmitted and the feedback received clock signals. An electronically controllable delay element is disposed within the transmission path of the clock signal on both the transmission leg and the return leg so that equal amounts of delay time may be added to the flight time in each direction. The delay may be electronically controlled to bring a "Transmitted Clock" pulse and a "Received Clock" pulse into phase. By insuring that the delay time for the entire transmission of the circuit by a particular clock pulse is an even number of cycle times, the master clock node on the clocked chip also may be controlled to be in phase with the "Transmitted Clock" pulse signal. This may be accomplished by initially calibrating the system at one-half of normal operating frequency and bringing "Transmitted Clock" pulse and "Received Clock" or feedback pulse into phase. Thereafter, upon returning to normal operating frequency, there always will be an even integral number of cycles of time delay between the transmission of the clock pulse by the oscillator and the receipt of that identical clock pulse by the phase detector; additionally, the pulse at the master clock mode will be in phase.
摘要翻译：描述了谐振时钟系统，其利用来自时钟芯片上的主时钟节点的反馈时钟信号，并且其中用相位检测器检测反馈时钟信号，以确定所发射的反馈和反馈接收的时钟信号的相关定相。电子可控延迟元件设置在传输腿和返回腿上的时钟信号的传输路径内，使得可以在每个方向上将等量的延迟时间添加到飞行时间。延迟可以被电子控制以使“发送时钟”脉冲和“接收时钟”脉冲进入相位。通过确保通过特定时钟脉冲整个电路传输的延迟时间是偶数个周期时间，时钟芯片上的主时钟节点也可以被控制为与“发送时钟”脉冲信号同相。这可以通过在正常工作频率的一半初始校准系统并且将“发送时钟”脉冲和“接收时钟”或反馈脉冲进入相位来实现。此后，在返回到正常工作频率之后，在振荡器发送时钟脉冲和由相位检测器接收到相同的时钟脉冲之间总是有一个偶数个周期的时间延迟; 此外，主时钟模式下的脉冲将同相。

14. 发明授权

US5299136A Fully testable DCVS circuits with single-track global wiring 失效
标题翻译：具有单轨全球接线的完全可测试的DCVS电路
公开(公告)号：US5299136A
公开(公告)日：1994-03-29
申请号：US711466
申请日：1991-06-05
申请人： Jacquelin Babakanian , James W. Davis , Mark S. Garvin , Robert M. Swanson , Nandor G. Thoma , David M. Wu
发明人： Jacquelin Babakanian , James W. Davis , Mark S. Garvin , Robert M. Swanson , Nandor G. Thoma , David M. Wu
IPC分类号： G01R31/28 , G01R31/3185 , H03K19/00 , H03K19/0944 , H03K19/173 , G06F15/20
CPC分类号： G01R31/318536 , H03K19/1738
摘要： Groups of DCVS (Differential Cascode Voltage Switch) circuits are interconnected by single-track data transfer connections. Each group contains one or more DCVS tree circuits, through which data signals propagate only on dual-track connections. In each group, at least one DCVS tree circuit is configured as an input boundary tree, and at least one tree circuit is configured as an output boundary tree. All data inputs externally applied to a group, are transferred only through input boundary trees of the group, and all data outputs transferred out of a group leave the group only through output boundary trees of the group. If a group has only a single tree, that tree serves as input and output boundary tree of the group. Each input boundary tree of each group has one or more associated primary shift register latch (SRL) circuits through which all external data inputs to that tree are transferred. Such external data inputs are received through the single-track connections mentioned above. The primary SRL circuits are also used to present predeterminable test data inputs to respective trees, and to collect primary test data outputs representing signals received through the single-track connections. In such usage, the SRL circuits are connected as a scannable shift register. Each output boundary tree has an exclusive-OR (XOR) circuit for indicating if the respective tree is in a legal or illegal state. The XOR circuits connect to secondary scannable SRL circuits for external presentation of illegal state indication. The primary test data outputs together with the externally presented illegal state indications form a basis for detecting and locating any faulty state in any group.
摘要翻译： DCVS（差分串联电压开关）电路组通过单轨数据传输连接相互连接。每组包含一个或多个DCVS树电路，数据信号仅通过双路连接传播。在每个组中，至少一个DCVS树电路被配置为输入边界树，并且至少一个树电路被配置为输出边界树。外部应用于组的所有数据输入仅通过组的输入边界树进行传输，并且从组中传出的所有数据输出仅通过组的输出边界树离开组。如果一个组只有一棵树，则该树用作该组的输入和输出边界树。每个组的每个输入边界树具有一个或多个相关联的主移位寄存器锁存（SRL）电路，通过该电路，传输该树的所有外部数据输入。这样的外部数据输入通过上述单轨连接来接收。主要的SRL电路还用于向各树提供可预测的测试数据输入，并收集表示通过单轨道连接接收的信号的主要测试数据输出。在这种使用中，SRL电路作为可扫描移位寄存器连接。每个输出边界树具有异或（XOR）电路，用于指示相应的树是否处于合法或非法状态。 XOR电路连接到二次可扫描的SRL电路，用于外部呈现非法状态指示。主要测试数据输出与外部提供的非法状态指示一起构成检测和定位任何组中任何故障状态的基础。

15. 发明授权

US4947369A Microword generation mechanism utilizing a separate branch decision programmable logic array 失效
标题翻译：微剑生成机制利用单独的分支决策可编程逻辑阵列
公开(公告)号：US4947369A
公开(公告)日：1990-08-07
申请号：US416881
申请日：1989-10-04
申请人： Nandor G. Thoma , Victor S. Moore , Wayne R. Kraft
发明人： Nandor G. Thoma , Victor S. Moore , Wayne R. Kraft
IPC分类号： G06F9/26 , G06F9/42
CPC分类号： G06F9/264
摘要： A microword generation mechanism is provided for producing the sequences of microwords used to control the execution of processor instructions in a microprogrammed digital data processor. This microword generation mechanism includes programmable logic array means responsive to the processor instructions for producing the appropriate microword sequences. The microword generation mechanism also includes condition indicator circuitry for supplying indicator signals indicating whether the results of arithmetic and logic operations in the processor meet certain types of conditions. The microword generation mechanism further includes a condition testing programmable logic array responsive to the condition field of a conditional branch type processor instruction for testing the appropriate indicator signal or signals and causing a branch type microword sequence to be produced if the specified condition is met.
摘要翻译：提供了一种微词生成机制，用于产生用于控制微程序数字数据处理器中的处理器指令的执行的微词序列。该微词生成机制包括响应于处理器指令以产生适当的微词序列的可编程逻辑阵列装置。微字生成机构还包括用于提供指示信号的条件指示器电路，其指示处理器中的算术和逻辑运算的结果是否符合某些类型的条件。微字生成机构还包括响应于条件分支型处理器指令的条件字段的条件测试可编程逻辑阵列，用于测试适当的指示符信号或者如果满足指定条件则产生分支型微字序列。

16. 发明授权

US4608649A Differential cascode voltage switch (DCVS) master slice for high efficiency/custom density physical design 失效
标题翻译：差分共源共栅电压开关（DCVS）主片用于高效率/定制密度物理设计
公开(公告)号：US4608649A
公开(公告)日：1986-08-26
申请号：US508451
申请日：1983-06-27
申请人： James W. Davis , Victor S. Moore , Nandor G. Thoma
发明人： James W. Davis , Victor S. Moore , Nandor G. Thoma
IPC分类号： G06F17/50 , H01L27/118 , H03K19/173 , H03K19/094
CPC分类号： H01L27/11803 , G06F17/5068 , H03K19/1738
摘要： A topological physical circuit design is utilized for the support of a Differential Cascode Voltage Switch circuit/logic technology in an Automated Placement-Wiring environment. This physical entity takes the form of a "brickwall" set of transistors in a Master Slice image which may be stored and later personalized.
摘要翻译：拓扑物理电路设计用于在自动放置布线环境中支持差分串联电压开关电路/逻辑技术。该物理实体采用可以存储和稍后个性化的主切片图像中的“砖墙”一组晶体管的形式。

17. 发明授权

US5732233A High speed pipeline method and apparatus 失效
标题翻译：高速管道方法及装置
公开(公告)号：US5732233A
公开(公告)日：1998-03-24
申请号：US376706
申请日：1995-01-23
申请人： Peter Juergen Klim , Nandor G. Thoma
发明人： Peter Juergen Klim , Nandor G. Thoma
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3869
摘要： A data processing apparatus has a number of data processors connected in a series by data lines so that data signals are processed in a preceding processor and communicated to a succeeding processor in the series. The apparatus has a number of control elements, where a control element has first and second inputs receiving processor status signals and an output sending a signal to enable processing. The control element output assumes a certain output state only if both inputs assume the state. The output, having assumed the state, holds the state, despite one of the inputs not holding the state, only if a certain one of the inputs does hold the state.
摘要翻译：数据处理装置具有通过数据线串联连接的多个数据处理装置，使得数据信号在前一处理器中被处理并且被传送到该系列中的后续处理器。该装置具有多个控制元件，其中控制元件具有接收处理器状态信号的第一和第二输入端以及发送信号以使能处理的输出。仅当两个输入都处于该状态时，控制元件输出才会产生一定的输出状态。假设状态的输出保持状态，尽管其中一个输入不保持状态，只有某一个输入确实保持状态。

18. 发明授权

US5524035A Symmetric clock system for a data processing system including dynamically switchable frequency divider 失效
标题翻译：用于数据处理系统的对称时钟系统，包括动态切换分频器
公开(公告)号：US5524035A
公开(公告)日：1996-06-04
申请号：US513245
申请日：1995-08-10
申请人： Humberto F. Casal , Rafey Mahmud , Trong Nguyen , Mark L. Shulman , Nandor G. Thoma
发明人： Humberto F. Casal , Rafey Mahmud , Trong Nguyen , Mark L. Shulman , Nandor G. Thoma
IPC分类号： H03K5/156 , H03K21/10 , H03K23/66 , H03K21/00
CPC分类号： H03K23/66 , H03K21/10 , H03K5/1565
摘要： A dynamically switchable clock system having a symmetrical output signal includes a frequency doubler which couples the input frequency to provide greater resolution and synchronization of an output signal to an input signal in the frequency divider and the facility to handle odd divides as even divides at double frequency, a counter controlled by a divisor select signal, first and second compare circuits which compare against the preprogrammed count for division, the compare circuits receiving an input from the divisor select circuits, and having outputs to a counter reset line and to an output clock S/R latch which provides the frequency divided symmetrical output signal.
摘要翻译：具有对称输出信号的可动态切换时钟系统包括倍频器，其耦合输入频率以提供输出信号与分频器中的输入信号的更高分辨率和同步，以及处理奇数分频的设备，以便以双倍频均匀分频，由除数选择信号控制的计数器，与预分频计数进行比较的第一和第二比较电路，比较电路接收来自除数选择电路的输入，并具有输出到计数器复位线和输出时钟S / R锁存器，提供分频对称的输出信号。

19. 发明授权

US5272397A Basic DCVS circuits with dual function load circuits 失效
标题翻译：具有双功能负载电路的基本DCVS电路
公开(公告)号：US5272397A
公开(公告)日：1993-12-21
申请号：US858790
申请日：1992-03-27
申请人： Imin P. Chen , James W. Davis , Robert M. Swanson , Nandor G. Thoma , David M. Wu
发明人： Imin P. Chen , James W. Davis , Robert M. Swanson , Nandor G. Thoma , David M. Wu
IPC分类号： G01R31/28 , H03K3/356 , H03K19/0948 , H03K19/173 , H03K19/20
CPC分类号： H03K19/1738 , H03K3/35613
摘要： Disclosed is a basic DCVS (differential cascode voltage switch) tree construct, which can be used as a uniform basis for constructing DCVS logic circuits, register-latch circuits and circuits which can be conditioned individually to function as either or both DCVS logic and register-latches. In addition to logic and load sections that may be identical to corresponding sections of prior art DCVS trees, this construct contains gating elements for providing unique functions of isolation, precharge support and latch input coupling. The isolation function is used to electrically isolate the logic and load sections from each other, so that each section can be made to operate in a mode which is independent of the other section. The precharge support function allows precharging of circuits in the logic section without involvement of the load section. The latch input coupling function allows signals to be applied to and latched in the load section from a source other than the respective logic section. Use of arrays of such trees for constructing complex logic circuits is described.

20. 发明授权

US5166547A Programmable DCVS logic circuits 失效
标题翻译：可编程DCVS逻辑电路
公开(公告)号：US5166547A
公开(公告)日：1992-11-24
申请号：US711487
申请日：1991-06-05
申请人： Jacquelin Babakanian , James W. Davis , Mark S. Garvin , Kim P. Liew , Yoav Medan , Nandor G. Thoma
发明人： Jacquelin Babakanian , James W. Davis , Mark S. Garvin , Kim P. Liew , Yoav Medan , Nandor G. Thoma
IPC分类号： H01L21/82 , H01L23/525 , H01L27/118 , H03K19/0952 , H03K19/173
CPC分类号： H01L23/5258 , H03K19/1735 , H03K19/1738 , H01L2924/0002 , H01L2924/3011
摘要： A basic tree construction, from which differential cascode voltage switch (DCVS) circuits having variable logic personality can be formed, contains n (>2) rows of differentially associated semiconductor device pairs spanned by n pairs of complementary input conductor leads, and a load circuit coupled to drain terminals of devices in the nth row. The nth row contains 2 device pairs and each other row contains 2.sup.i-1 device pairs (i=1, 2, . . . , n-1). Connections between source and drain terminals of devices in successive rows are predefined from the 1st to the n-1st row and variably definable between the n-1st and nth rows. Connections between input conductors and device gate terminals are predefined in each row other than the nth row, and variably definable in the nth row. Upon selectively defining a set of variable connections relative to the n-1st and nth rows the logic personality of the tree is selected to conform to any one of all possible functions of n variables. Logic function personalization is established in one embodiment by altering materials at discrete points in a space between n-1st and nth rows. In another embodiment, personalization is established by altering signals stored by latch devices in the space between the n-1st and nth rows which control gating device adjacently positioned to form conductive connections corresponding to those formed by altering materials in the first embodiment.
摘要翻译：可以形成具有可变逻辑特性的差分共源共栅电压开关（DCVS）电路的基本树结构包含由n对互补输入导体引线跨越的n（> 2）个由差分相关的半导体器件对构成的行，负载电路耦合到第n行的器件的漏极端子。第n行包含2个设备对，每行包含2i-1个设备对（i = 1,2，...，n-1）。在连续行中的设备的源极和漏极端子之间的连接从第一行到第n行预定义，并且可以在第n-1行和第n行之间可变地定义。输入导体和器件栅极端子之间的连接在除第n行以外的每行中预定义，并且在第n行中可变地定义。在选择性地定义相对于第n-1和n行的一组可变连接时，选择树的逻辑个性以符合n个变量的所有可能函数中的任何一个。在一个实施例中通过在第n-1和第n行之间的空间中的离散点处改变材料来建立逻辑功能个性化。在另一个实施例中，通过在第n-1行和第n行之间的空间中改变由锁存装置存储的信号来建立个性化，所述信号控制门控装置相邻定位以形成对应于在第一实施例中通过改变材料形成的导电连接的导电连接。

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