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11. 发明申请

US20060224833A1 Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache state 有权
公开(公告)号：US20060224833A1
公开(公告)日：2006-10-05
申请号：US11095734
申请日：2005-03-31
申请人： Guy Guthrie , Aaron Sawdey , William Starke , Jeffrey Stuecheli
发明人： Guy Guthrie , Aaron Sawdey , William Starke , Jeffrey Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F12/0811 , G06F12/0815 , G06F12/0831
摘要： In response to a master receiving a memory access request indicating a target address, the master accesses a first cache directory of an upper level cache of a cache hierarchy. In response to the target address being associated in the first cache directory with an entry having a valid address tag and a first invalid coherency state, the master issues a request specifying the target address on an interconnect fabric without regard to a coherency state associated with the target address in a second cache directory of a lower level cache of the cache hierarchy. In response to the target address having a second invalid coherency state with respect to the first cache directory, the master issues a request specifying the target address on an interconnect fabric after determining a coherency state associated with the target address in the second cache directory of the lower level cache of the cache hierarchy.

12. 发明申请

US20070294486A1 Reducing Number of Rejected Snoop Requests By Extending Time to Respond to Snoop Request 失效
标题翻译：通过延长响应Snoop请求的时间来减少被拒绝的侦听请求数
公开(公告)号：US20070294486A1
公开(公告)日：2007-12-20
申请号：US11847941
申请日：2007-08-30
申请人： Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.
摘要翻译：用于减少拒绝的窥探请求数量的缓存，系统和方法。缓存中的“停止/重新排序单元”从互连中接收窥探请求。窥探请求的诸如地址的信息被存储在失速/重新排序单元的队列中。停止/重新排序单元将窥探请求转发到也从处理器接收请求的选择器。仲裁机制选择来自处理器的窥探请求或请求。如果侦听请求被仲裁机制拒绝，关于窥探请求的信息（例如地址）可以被保留在停止/重新排序单元中。请求可能会稍后重新发送到选择器。该过程可以重复直到“n”个时钟周期。通过提供窥探请求仲裁机制接受的额外机会（n个时钟周期），最终可能会拒绝更少的侦听请求。

13. 发明申请

US20070226427A1 Data processing system, cache system and method for updating an invalid coherency state in response to snooping an operation 失效
标题翻译：数据处理系统，缓存系统和用于响应于窥探操作来更新无效一致性状态的方法
公开(公告)号：US20070226427A1
公开(公告)日：2007-09-27
申请号：US11388017
申请日：2006-03-23
申请人： Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F2212/507
摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data. In response to snooping an exclusive access operation, the exclusive access request specifying a target address matching the address tag and indicating a relative domain location of a requester that initiated the exclusive access operation, the first cache memory updates the coherency state field from the first data-invalid coherency state to a second data-invalid coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, and whether a target memory block associated with the address tag is cached within the first coherency domain upon successful completion of the exclusive access operation based upon the relative location of the requestor.
摘要翻译：缓存相干数据处理系统至少包括第一和第二相干域。在数据处理系统的第一相关域内的第一高速缓冲存储器中，将与存储位置和地址标签相关联的一致性状态字段设置为指示地址标签有效的第一数据无效一致性状态，存储位置不包含有效数据。响应于窥探独占访问操作，专用访问请求指定与地址标签匹配的目标地址，并且指示发起独占访问操作的请求者的相对域位置，第一高速缓存存储器从第一数据更新相关性状态字段 - 无效的一致性状态到指示地址标签有效的第二数据无效一致性状态，存储位置不包含有效数据，以及与地址标签相关联的目标存储器块是否被缓存在第一相关域内基于请求者的相对位置成功完成独占访问操作。

14. 发明申请

US20060271744A1 Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a history-based prediction 失效
标题翻译：用于使用基于历史的预测来预测性地选择操作的广播范围的数据处理系统和方法
公开(公告)号：US20060271744A1
公开(公告)日：2006-11-30
申请号：US11140821
申请日：2005-05-31
申请人： Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0833 , G06F2212/507
摘要： According to a method of data processing, a predictor is maintained that indicates a historical scope of broadcast for one or more previous operations transmitted on an interconnect of a data processing system. A scope of broadcast of a subsequent operation is predictively selected by reference to the predictor.
摘要翻译：根据数据处理的方法，保持预测器，其指示在数据处理系统的互连上发送的一个或多个先前操作的广播的历史范围。通过参考预测器预测性地选择后续操作的广播范围。

15. 发明申请

US20070168618A1 Data processing system, cache system and method for precisely forming an invalid coherency state indicating a broadcast scope 失效
标题翻译：数据处理系统，缓存系统和精确形成指示广播范围的无效一致性状态的方法
公开(公告)号：US20070168618A1
公开(公告)日：2007-07-19
申请号：US11333615
申请日：2006-01-17
申请人： Leo Clark , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Leo Clark , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831
摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a memory block is held in a storage location associated with an address tag and a coherency state field. A determination is made if a home system memory assigned an address associated with the memory block is within the first coherency domain. If not, the coherency state field is set to a coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, the first coherency domain does not contain the home system memory, and that, following formation of the coherency state, the memory block is cached outside of the first coherency domain.
摘要翻译：缓存相干数据处理系统至少包括第一和第二相干域。在数据处理系统的第一相关域内的第一高速缓存存储器中，存储块被保存在与地址标签和一致性状态字段相关联的存储位置中。如果分配了与存储器块相关联的地址的归属系统存储器在第一相干域内，则确定。如果不是，则将一致性状态字段设置为指示地址标签有效的一致性状态，即存储位置不包含有效数据，第一相干域不包含家庭系统存储器，并且在形成一致性状态下，内存块被缓存在第一个相干域之外。

16. 发明申请

US20060277370A1 Data processing system and method for selectively updating an invalid coherency state in response to snooping a castout 有权
公开(公告)号：US20060277370A1
公开(公告)日：2006-12-07
申请号：US11146443
申请日：2005-06-06
申请人： Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813
摘要： In an entry of a first cache memory within a first coherency domain of a data processing system including at least first and second coherency domains, a coherency state field is set to a first state that indicates that an associated address tag is valid, an associated storage location does not contain valid data, and a memory block identified by the address tag is likely cached outside the first coherency domain. In response to snooping a castout operation, the first cache memory determines if the castout operation hits in the entry and, if so, updates the coherency state field from the first state to a second state indicating that the associated address tag is invalid.

17. 发明申请

US20060184748A1 Reducing number of rejected snoop requests by extending time to respond to snoop request 失效
公开(公告)号：US20060184748A1
公开(公告)日：2006-08-17
申请号：US11056740
申请日：2005-02-11
申请人： Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： Benjiman Goodman , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.

18. 发明申请

US20060179222A1 System bus structure for large L2 cache array topology with different latency domains 失效
标题翻译：具有不同延迟域的大二级缓存阵列拓扑的系统总线结构
公开(公告)号：US20060179222A1
公开(公告)日：2006-08-10
申请号：US11054925
申请日：2005-02-10
申请人： Vicente Chung , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： Vicente Chung , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/0851 , Y02D10/13
摘要： A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. In the illustrative embodiment a first input line is used for loading both a first byte array of the first cache line and a first byte array of the second cache line, a second input line is used for loading both a second byte array of the first cache line and a second byte array of the second cache line, and the transmission of the separate portions of the first and second memory values is interleaved between the first and second data busses. The first data bus can be one of a plurality of data busses in a first data bus set, and the second data bus can be one of a plurality of data busses in a second data bus set. Two address busses (one for each data bus set) are used to receive successive address tags that identify which portions of the requested memory values are being received from each data bus set. For example, the requested memory values may be 32 bytes each, and the separate portions of the requested memory values are received over four successive cycles with an 8-byte portion of each value received each cycle. The cache lines are spread across different cache sectors of the cache memory, wherein the cache sectors have different output latencies, and the separate portions of a given requested memory value are loaded sequentially into the corresponding cache sectors based on their respective output latencies. Merge flow circuits responsive to the cache controller are used to receive the portions of a requested memory value and input those bytes into the cache sector.
摘要翻译：一种高速缓冲存储器，其通过在连续时钟周期的第一时间间隔内从第一数据总线接收第一请求存储器值的分开的部分来将两个存储器值加载到两个高速缓存行中，并且从第二数据接收第二请求存储器值的分离部分总线与第一时间跨度重叠的连续时钟周期的第二时间跨度。在说明性实施例中，第一输入线用于加载第一高速缓存行的第一字节数组和第二高速缓存行的第一字节数组，第二输入行用于加载第一高速缓存的第二字节数组线和第二高速缓存线的第二字节阵列，并且第一和第二存储器值的分离部分的传输在第一和第二数据总线之间交错。第一数据总线可以是第一数据总线组中的多个数据总线之一，并且第二数据总线可以是第二数据总线组中的多个数据总线中的一个。两个地址总线（每个数据总线集合一个）用于接收连续的地址标签，其识别从每个数据总线组接收到所请求的存储器值的哪些部分。例如，所请求的存储器值可以是每个32个字节，并且所请求的存储器值的分开的部分在四个连续周期中被接收，每个周期接收每个值的8字节部分。高速缓存行分布在高速缓冲存储器的不同高速缓存扇区上，其中高速缓存扇区具有不同的输出延迟，并且给定请求的存储器值的分离部分基于它们各自的输出延迟顺序地加载到相应的高速缓存扇区中。响应于高速缓存控制器的合并流回路用于接收请求的存储器值的部分并将这些字节输入高速缓存扇区。

19. 发明申请

US20080016284A1 DATA PROCESSING SYSTEM AND METHOD FOR PREDICTIVELY SELECTING A SCOPE OF BROADCAST OF AN OPERATION UTILIZING A HISTORY-BASED PREDICTION 审中-公开
标题翻译：数据处理系统和方法，用于预测性地选择使用基于历史的预测操作的广播范围
公开(公告)号：US20080016284A1
公开(公告)日：2008-01-17
申请号：US11863979
申请日：2007-09-28
申请人： BENJIMAN GOODMAN , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
发明人： BENJIMAN GOODMAN , Guy Guthrie , William Starke , Jeffrey Stuecheli , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0833 , G06F2212/507
摘要： According to a method of data processing, a predictor is maintained that indicates a historical scope of broadcast for one or more previous operations transmitted on an interconnect of a data processing system. A scope of broadcast of a subsequent operation is predictively selected by reference to the predictor.
摘要翻译：根据数据处理的方法，保持预测器，其指示在数据处理系统的互连上发送的一个或多个先前操作的广播的历史范围。通过参考预测器预测性地选择后续操作的广播范围。

20. 发明申请

US20060179234A1 Cache member protection with partial make MRU allocation 失效
标题翻译：缓存成员保护部分使MRU分配
公开(公告)号：US20060179234A1
公开(公告)日：2006-08-10
申请号：US11054390
申请日：2005-02-09
申请人： Robert Bell , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： Robert Bell , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0897 , G06F12/123 , G06F12/128
摘要： A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of the member of the congruence class that is to be protected. A protected member is not removed from the cache during standard LRU victim selection, unless that member is invalid. The protection bits are pipelined to MRU update logic, where they are used to generate an MRU vector. The particular member identified by the MRU vector (and pointer) is protected from selection as the next LRU victim, unless the member is Invalid. The make MRU operation affects only the lower level LRU state bits arranged a tree-based structure and thus only negates the selection of the protected member, without affecting LRU victim selection of the other members.
摘要翻译：一种用于在LRU受害者选择期间能够保护缓存的特定成员的方法和装置。 LRU状态阵列除了状态位之外还包括额外的“保护”位。保护位用作用于标识要保护的同余类的成员的位置的指针。在标准LRU受害者选择期间，保护成员不会从缓存中删除，除非该成员无效。保护位被流水线到MRU更新逻辑，它们用于生成MRU向量。由MRU向量（和指针）标识的特定成员不被选择作为下一个LRU受害者，除非成员无效。使MRU操作仅影响布置了基于树的结构的较低级LRU状态位，并且因此仅在不影响其他成员的LRU受害者选择的情况下否定对被保护成员的选择。

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