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1. 发明申请

US20050193174A1 System bus read data transfers with data ordering control bits 失效
标题翻译：系统总线使用数据排序控制位读取数据传输
公开(公告)号：US20050193174A1
公开(公告)日：2005-09-01
申请号：US11041711
申请日：2005-01-22
申请人： Ravi Arimilli , Vicente Chung , Guy Guthrie , Jody Joyner
发明人： Ravi Arimilli , Vicente Chung , Guy Guthrie , Jody Joyner
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0831
摘要： A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to effectuate data transfer, determining at the system component logic the order in which to transmit data to the processor, and issuing to the data bus a selected order bit concurrent with the data, wherein the selected order bit alerts the processor of the order and the data is transmitted in that order. In a preferred embodiment, the system component is the cache and the method may involve receiving at the cache a preference of ordering for a read address/request from the processor. The preference order logic of the cache controller or a preference order logic component evaluates the preference of ordering desired by comparing the processor preference with other preferences, including cache order preference. One preference order is selected and the data is then retrieved from a cache line of the cache in the order selected.
摘要翻译：一种用于向处理器通知所选择的数据传输顺序的处理器的方法。该方法包括以下步骤：将系统组件经由数据总线耦合到处理器以实现数据传输，在系统组件逻辑处确定将数据发送到处理器的顺序，以及向数据总线发出与数据，其中所选择的订单位向处理器提醒订单，并且以该顺序传送数据。在优选实施例中，系统组件是高速缓存，并且该方法可以涉及在高速缓存处接收对来自处理器的读取地址/请求的排序的偏好。高速缓存控制器或偏好顺序逻辑组件的偏好顺序逻辑通过将处理器偏好与其他偏好（包括高速缓存顺序偏好）进行比较来评估期望的顺序的偏好。选择一个偏好顺序，然后以所选顺序从高速缓存的高速缓存行检索数据。

2. 发明申请

US20060179222A1 System bus structure for large L2 cache array topology with different latency domains 失效
标题翻译：具有不同延迟域的大二级缓存阵列拓扑的系统总线结构
公开(公告)号：US20060179222A1
公开(公告)日：2006-08-10
申请号：US11054925
申请日：2005-02-10
申请人： Vicente Chung , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： Vicente Chung , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/0851 , Y02D10/13
摘要： A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a second time span of successive clock cycles which overlaps with the first time span. In the illustrative embodiment a first input line is used for loading both a first byte array of the first cache line and a first byte array of the second cache line, a second input line is used for loading both a second byte array of the first cache line and a second byte array of the second cache line, and the transmission of the separate portions of the first and second memory values is interleaved between the first and second data busses. The first data bus can be one of a plurality of data busses in a first data bus set, and the second data bus can be one of a plurality of data busses in a second data bus set. Two address busses (one for each data bus set) are used to receive successive address tags that identify which portions of the requested memory values are being received from each data bus set. For example, the requested memory values may be 32 bytes each, and the separate portions of the requested memory values are received over four successive cycles with an 8-byte portion of each value received each cycle. The cache lines are spread across different cache sectors of the cache memory, wherein the cache sectors have different output latencies, and the separate portions of a given requested memory value are loaded sequentially into the corresponding cache sectors based on their respective output latencies. Merge flow circuits responsive to the cache controller are used to receive the portions of a requested memory value and input those bytes into the cache sector.
摘要翻译：一种高速缓冲存储器，其通过在连续时钟周期的第一时间间隔内从第一数据总线接收第一请求存储器值的分开的部分来将两个存储器值加载到两个高速缓存行中，并且从第二数据接收第二请求存储器值的分离部分总线与第一时间跨度重叠的连续时钟周期的第二时间跨度。在说明性实施例中，第一输入线用于加载第一高速缓存行的第一字节数组和第二高速缓存行的第一字节数组，第二输入行用于加载第一高速缓存的第二字节数组线和第二高速缓存线的第二字节阵列，并且第一和第二存储器值的分离部分的传输在第一和第二数据总线之间交错。第一数据总线可以是第一数据总线组中的多个数据总线之一，并且第二数据总线可以是第二数据总线组中的多个数据总线中的一个。两个地址总线（每个数据总线集合一个）用于接收连续的地址标签，其识别从每个数据总线组接收到所请求的存储器值的哪些部分。例如，所请求的存储器值可以是每个32个字节，并且所请求的存储器值的分开的部分在四个连续周期中被接收，每个周期接收每个值的8字节部分。高速缓存行分布在高速缓冲存储器的不同高速缓存扇区上，其中高速缓存扇区具有不同的输出延迟，并且给定请求的存储器值的分离部分基于它们各自的输出延迟顺序地加载到相应的高速缓存扇区中。响应于高速缓存控制器的合并流回路用于接收请求的存储器值的部分并将这些字节输入高速缓存扇区。

3. 发明申请

US20050149660A1 Multiprocessor data processing system having a data routing mechanism regulated through control communication 失效
标题翻译：具有通过控制通信调节的数据路由机制的多处理器数据处理系统
公开(公告)号：US20050149660A1
公开(公告)日：2005-07-07
申请号：US10752835
申请日：2004-01-07
申请人： Ravi Arimilli , Jerry Lewis , Vicente Chung , Jody Joyner
发明人： Ravi Arimilli , Jerry Lewis , Vicente Chung , Jody Joyner
IPC分类号： G06F13/00 , G06F13/40 , G06F15/163
CPC分类号： G06F13/4027
摘要： A data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one implementation, a data processing system includes at least first through third processing units, data storage coupled to the plurality of processing units, and an interconnect fabric. The interconnect fabric includes at least a first data bus coupling the first processing unit to the second processing unit and a second data bus coupling the third processing unit to the second processing unit so that the first and third processing units can transmit data traffic to the second processing unit. The data processing system further includes a control channel coupling the first and third processing units. The first processing unit requests approval from the third processing unit via the control channel to transmit a data communication to the second processing unit, and the third processing unit approves or delays transmission of the data communication in a response transmitted via the control channel.
摘要翻译：数据互连和路由机制减少数据通信延迟，支持基于处理器活动级别/流量的动态路由确定，并实现支持通信频率可扩展改进的架构。在一个实现中，数据处理系统至少包括第一到第三处理单元，耦合到多个处理单元的数据存储器和互连结构。所述互连结构至少包括将所述第一处理单元耦合到所述第二处理单元的第一数据总线和将所述第三处理单元耦合到所述第二处理单元的第二数据总线，使得所述第一处理单元和所述第三处理单元可以向第二处理单元处理单元。数据处理系统还包括耦合第一和第三处理单元的控制通道。第一处理单元经由控制信道从第三处理单元请求批准，以将数据通信发送到第二处理单元，并且第三处理单元在经由控制信道发送的响应中批准或延迟数据通信的传输。

4. 发明申请

US20070073998A1 Data processing system, method and interconnect fabric supporting high bandwidth communication between nodes 失效
标题翻译：支持节点之间高带宽通信的数据处理系统，方法和互连结构
公开(公告)号：US20070073998A1
公开(公告)日：2007-03-29
申请号：US11236458
申请日：2005-09-27
申请人： Vicente Chung , Benjiman Goodman , Praveen Reddy , William Starke
发明人： Vicente Chung , Benjiman Goodman , Praveen Reddy , William Starke
IPC分类号： G06F15/00
CPC分类号： G06F15/17337
摘要： A data processing system includes a first processing node and a second processing node. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second processing units coupled to each other for communication. Each of the plurality of first processing units is coupled to a respective one of the plurality of second processing units in the second processing node by a respective one of a plurality of point-to-point links.
摘要翻译：数据处理系统包括第一处理节点和第二处理节点。第一处理节点包括彼此耦合以进行通信的多个第一处理单元，并且第二处理节点包括彼此耦合以进行通信的多个第二处理单元。多个第一处理单元中的每一个通过多个点对点链接中的相应一个耦合到第二处理节点中的多个第二处理单元中的相应一个。

5. 发明申请

US20060179197A1 Data processing system, method and interconnect fabric having a partial response rebroadcast 审中-公开
标题翻译：具有部分响应重播的数据处理系统，方法和互连结构
公开(公告)号：US20060179197A1
公开(公告)日：2006-08-10
申请号：US11055036
申请日：2005-02-10
申请人： Vicente Chung , Benjiman Goodman
发明人： Vicente Chung , Benjiman Goodman
IPC分类号： G06F13/14
CPC分类号： G06F13/1663 , G06F12/0813 , G06F12/0831
摘要： A data processing system includes a plurality of processing units coupled for communication. The plurality of processing units includes at least a local hub and a local master. The local master includes a master that issues a request for access to a memory block and interconnect logic coupled to at least one communication link coupling the local master to the local hub. The interconnect logic includes partial response logic that synchronizes internal transmission of a first partial response of a snooper to the request with receipt, via the at least one communication link, of a second partial response to the request from the local hub.
摘要翻译：数据处理系统包括耦合用于通信的多个处理单元。多个处理单元至少包括本地集线器和本地主机。本地主机包括主机，其发出对存储器块的访问请求，并将耦合到至少一个将本地主机耦合到本地集线器的通信链路的逻辑互连逻辑。所述互连逻辑包括部分响应逻辑，其使所述窥探者的所述第一部分响应的内部传输与所述请求同步，所述内部传输经由所述至少一个通信链路从所述本地集线器接收对所述请求的第二部分响应。

6. 发明申请

US20050149692A1 Multiprocessor data processing system having scalable data interconnect and data routing mechanism 失效
标题翻译：具有可扩展数据互连和数据路由机制的多处理器数据处理系统
公开(公告)号：US20050149692A1
公开(公告)日：2005-07-07
申请号：US10752959
申请日：2004-01-07
申请人： Ravi Arimilli , Jerry Lewis , Vicente Chung , Jody Joyner
发明人： Ravi Arimilli , Jerry Lewis , Vicente Chung , Jody Joyner
IPC分类号： G06F15/00 , G06F15/163 , G06F15/173
CPC分类号： G06F15/17381
摘要： The data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one application, a data processing system includes first and second processing books, each including at least first and second processing units. Each of the first and second processing units has a respective first output data bus. The first output data bus of the first processing unit is coupled to the second processing unit, and the first output data bus of the second processing unit is coupled to the first processing unit. At least the first processing unit of the first processing book and the second processing unit of the second processing book each have a respective second output data bus. The second output data bus of the first processing unit of the first processing book is coupled to the first processing unit of the second processor book, and the second output data bus of the second processing unit of the second processor book is coupled to the second processing unit of the first processor book.
摘要翻译：数据互连和路由机制减少数据通信延迟，支持基于处理器活动级别/流量的动态路由确定，并实现支持通信频率可扩展改进的架构。在一个应用中，数据处理系统包括第一和第二处理簿，每个书籍至少包括第一和第二处理单元。第一和第二处理单元中的每一个具有相应的第一输出数据总线。第一处理单元的第一输出数据总线耦合到第二处理单元，第二处理单元的第一输出数据总线耦合到第一处理单元。至少第一处理簿的第一处理单元和第二处理簿的第二处理单元各自具有相应的第二输出数据总线。第一处理簿的第一处理单元的第二输出数据总线耦合到第二处理器书的第一处理单元，第二处理器书的第二处理单元的第二输出数据总线耦合到第二处理器第一个处理器书的单位。

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