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11. 发明申请

US20060001058A1 Fin field effect transistor memory cell 审中-公开
标题翻译： Fin场效应晶体管存储单元
公开(公告)号：US20060001058A1
公开(公告)日：2006-01-05
申请号：US11157496
申请日：2005-06-20
申请人： Lars Dreeskornfeld , Jessica Hartwich , Franz Hofmann , Johannes Kretz , Michael Specht
发明人： Lars Dreeskornfeld , Jessica Hartwich , Franz Hofmann , Johannes Kretz , Michael Specht
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/42384 , H01L27/115 , H01L27/11568 , H01L29/40117 , H01L29/66795 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： A fin field effect transistor memory cell having a first and a second source/drain region, a gate region, a semiconductor fin having a channel region between the first and the second source/drain region, a charge storage layer configured as a trapping layer arranged at least partly on the gate region, and a word line region on at least one part of the charge storage layer. The charge storage layer is set up such that electrical charge carriers can be selectively introduced into the charge storage layer or be removed therefrom by applying predetermined electrical potentials to the fin field effect transistor memory cell.
摘要翻译：具有第一和第二源极/漏极区域的栅极场效应晶体管存储单元，栅极区域，具有在第一和第二源极/漏极区域之间的沟道区域的半导体鳍片，被配置为俘获层的电荷存储层，至少部分地在栅极区域上，以及电荷存储层的至少一部分上的字线区域。电荷存储层被设置成使得电荷载流子可以选择性地引入电荷存储层中，或者通过向鳍式场效应晶体管存储单元施加预定的电位而将其移除。

12. 发明申请

US20050224888A1 Integrated circuit array 审中-公开
标题翻译：集成电路阵列
公开(公告)号：US20050224888A1
公开(公告)日：2005-10-13
申请号：US11116139
申请日：2005-04-27
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landgraf , Richard Luyken , Wolfgang Roesner , Thomas Schulz , Michael Specht
IPC分类号： G11C13/02 , H01L29/78 , H01L51/00 , H01L51/30 , H01L29/76
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/17 , H01L27/283 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： Integrated circuit array having field effect transistors (FETs) formed next to and/or above one another. The array has a substrate, a planarized first wiring plane with interconnects and first source/drain regions of the FETs, a planarized first insulator layer on the first wiring plane, a planarized gate region layer, which has patterned gate regions made of electrically conductive material and insulator material introduced therebetween, on the first insulated layer, a planarized second insulator layer on the gate region layer, holes formed through the second insulator layer, the gate regions, and the first insulator layer, a vertical nanoelement serving as a channel region in each of the holes, a second wiring plane with interconnects and second source/drain regions of the FETs, each nanoelement being arranged between the first and second wiring planes, and a gate insulating layer between the respective vertical nanoelement and the electrically conductive material of the gate regions.
摘要翻译：集成电路阵列具有形成在彼此之上和/或彼此之上的场效应晶体管（FET）。阵列具有衬底，具有互连的平坦化的第一布线面和FET的第一源极/漏极区，在第一布线平面上的平坦化的第一绝缘体层，平坦化的栅极区域层，其具有由导电材料制成的图案化栅极区域和介于其间的绝缘体材料，在所述第一绝缘层上，在所述栅极区域层上的平坦化的第二绝缘体层，穿过所述第二绝缘体层，所述栅极区域和所述第一绝缘体层形成的空穴，用作所述沟道区域中的沟道区域的垂直纳米元件每个孔，具有互连的第二布线面和FET的第二源极/漏极区，每个纳米元件布置在第一和第二布线平面之间，并且在相应的垂直纳米元件和导电材料之间的栅极绝缘层门区域。

13. 发明申请

US20050201187A1 Integrated read-only memory, method for operating said read-only memory and corresponding production method 有权
标题翻译：集成只读存储器，用于操作所述只读存储器的方法和相应的制造方法
公开(公告)号：US20050201187A1
公开(公告)日：2005-09-15
申请号：US10505320
申请日：2003-02-17
申请人： Franz Hofmann , Richard Luyken , Till Schlosser
发明人： Franz Hofmann , Richard Luyken , Till Schlosser
IPC分类号： H01L27/10 , G11C8/02 , G11C16/02 , G11C16/10 , H01L21/8247 , H01L27/115 , H01L27/24 , H01L27/28
CPC分类号： H01L27/28 , H01L27/2436 , H01L27/2454 , H01L27/2472 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/14 , H01L45/147
摘要： An integrated read-only memory having select transistors, each of which has a drain connection and an electrode connection for feeding an electrical signal such as a voltage or a current. A layer is provided between the drain connections and the electrode, whose electric resistance can be changed under the effect of a configuration voltage or current. The layer may be applied in a backend process.
摘要翻译：具有选择晶体管的集成只读存储器，每个具有漏极连接和用于馈送诸如电压或电流的电信号的电极连接。在漏极连接和电极之间设置一层，其电阻可以在配置电压或电流的作用下改变。该层可以应用在后端进程中。

14. 发明申请

US20050199942A1 Semiconductor memory with vertical memory transistors and method for fabricating it 有权
标题翻译：具有垂直存储晶体管的半导体存储器及其制造方法
公开(公告)号：US20050199942A1
公开(公告)日：2005-09-15
申请号：US11073205
申请日：2005-03-05
申请人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Thomas Schulz , Michael Specht
发明人： Franz Hofmann , Erhard Landgraf , Richard Luyken , Thomas Schulz , Michael Specht
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/792
CPC分类号： H01L21/28282 , H01L29/66833 , H01L29/792 , H01L29/7923 , H01L29/7926
摘要： The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory generally includes a semiconductor layer arranged on a substrate surface that includes a normally positioned step between a deeper region and a higher region. The semiconductor memory further includes doped contact regions, channel regions, a trapping layer arranged on a gate oxide layer, and at least one gate electrode. The method for forming the memory cells includes patterning a semiconductor layer to form a deeper semiconductor region and a higher semiconductor region having a step positioned between the regions. The method further includes forming a first oxide layer and a trapping layer, and then removing portions of the trapping layer and the first oxide layer and applying a second oxide layer at least regions of a doped region, the trapping layer, and the step area, and applying a gate electrode to the second oxide layer and doping, at least in regions, of the deeper semiconductor region and the higher semiconductor region to form a deeper contact region and a higher contact region.
摘要翻译：本发明涉及具有多个存储单元的半导体存储器和用于形成存储单元的方法。半导体存储器通常包括布置在衬底表面上的半导体层，其包括较深区域和较高区域之间的正常定位的台阶。半导体存储器还包括掺杂接触区域，沟道区域，布置在栅极氧化物层上的俘获层和至少一个栅电极。形成存储单元的方法包括图案化半导体层以形成较深的半导体区域和具有位于该区域之间的台阶的较高半导体区域。该方法还包括形成第一氧化物层和俘获层，然后去除俘获层和第一氧化物层的部分，并且至少在掺杂区域，俘获层和台阶区域的区域上施加第二氧化物层，以及向所述第二氧化物层施加栅电极，并且至少在所述较深半导体区域和所述较高半导体区域的区域中掺杂以形成更深的接触区域和更高的接触区域。

15. 发明授权

US06914292B2 Floating gate field-effect transistor 失效
标题翻译：浮栅场效应晶体管
公开(公告)号：US06914292B2
公开(公告)日：2005-07-05
申请号：US10302615
申请日：2002-11-21
申请人： Michael Specht , Martin Städele , Wolfgang Rösner , Franz Hofmann
发明人： Michael Specht , Martin Städele , Wolfgang Rösner , Franz Hofmann
IPC分类号： H01L21/8247 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28194 , H01L29/42324 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7883
摘要： A floating gate field-effect transistor (400), which is preferably used as a memory cell, has, above or below a floating gate region (407), an electrically insulating layer sequence (408) having a lower layer (409) having a first relative permittivity, having a middle layer (410) having a second relative permittivity, and having an upper layer (411) having a third relative permittivity, the second relative permittivity being greater than the first relative permittivity and greater than the third relative permittivity.
摘要翻译：优选用作存储单元的浮置栅极场效应晶体管（400）具有在浮置栅极区域（407）的上方或下方的具有下层（409）的电绝缘层序列（408），其具有具有第二相对介电常数的中间层（410）和具有第三相对介电常数的上层（411）的第一相对介电常数，第二相对介电常数大于第一相对介电常数且大于第三相对介电常数。

16. 发明申请

US20050100938A1 Vertical impedance sensor arrangement and method for producing a vertical impedance sensor arrangement 审中-公开
标题翻译：垂直阻抗传感器布置和垂直阻抗传感器布置方法
公开(公告)号：US20050100938A1
公开(公告)日：2005-05-12
申请号：US10939319
申请日：2004-09-09
申请人： Franz Hofmann , Richard Luyken , Wolfgang Roesner
发明人： Franz Hofmann , Richard Luyken , Wolfgang Roesner
IPC分类号： C12Q1/68 , G01N33/543
CPC分类号： G01N33/54386 , G01N27/3276
摘要： Vertical impedance sensor arrangement including a substrate, a first electrically conductive structure having a first uncovered surface and being arranged in and/or on the substrate, a spacer arranged above the substrate and/or at least partially on the first electrically conductive structure, a second electrically conductive structure having a second uncovered surface and being arranged on the spacer, and capture molecules, which are immobilized on the first and on the second uncovered surface, are set up such that particles to be detected hybridize with the capture molecules. The spacer is formed separately from the substrate, and the thickness of the spacer is defined by means of a deposition method.
摘要翻译：垂直阻抗传感器布置包括基底，具有第一未覆盖表面并布置在基底中和/或基底上的第一导电结构，布置在基底上和/或至少部分地在第一导电结构上的间隔物，第二具有第二未覆盖表面并布置在间隔物上的导电结构，并且被固定在第一和第二未覆盖表面上的捕获分子被设置成使得待检测的颗粒与捕获分子杂交。间隔物与衬底分开形成，并且通过沉积方法限定间隔物的厚度。

17. 发明申请

US20050032311A1 Fabrication method for memory cell 失效
标题翻译：存储单元制造方法
公开(公告)号：US20050032311A1
公开(公告)日：2005-02-10
申请号：US10899436
申请日：2004-07-26
申请人： Franz Hofmann , Erhard Landgraf , Hannes Luyken
发明人： Franz Hofmann , Erhard Landgraf , Hannes Luyken
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： Method of fabricating a memory cell, in which a storage layer, which is designed for programming by charge carrier trapping, and a gate electrode, which is electrically insulated from a semiconductor material, are fabricated at a top side of a semiconductor body or a semiconductor layer structure above a channel region provided between doped source-drain regions. The method includes the steps of fabricating at least one trench in the top side, providing at least portions of the trench walls which adjoin the source-drain regions to be fabricated with the storage layer, depositing a material provided for the gate electrode into the trench, forming the source-drain regions by covering the gate electrode, removing, on both sides of the trench, the semiconductor material down to an intended depth, and implanting dopant, and applying an insulation layer to the source-drain region, and fabricating an electrical connection for the gate electrode.
摘要翻译：制造存储单元的方法，其中设计用于通过电荷载流子捕获进行编程的存储层和与半导体材料电绝缘的栅电极制造在半导体本体或半导体的顶侧在设置在掺杂源极 - 漏极区之间的沟道区域之上的层结构。该方法包括以下步骤：在顶侧制造至少一个沟槽，提供沟槽壁的至少部分，其邻接待制造的源极 - 漏极区域与存储层，将为栅电极提供的材料沉积到沟槽通过覆盖栅极电极形成源极 - 漏极区域，在沟槽的两侧将半导体材料去除到预期深度，并且注入掺杂剂，并且向源极 - 漏极区域施加绝缘层，并且制造栅电极的电连接。

18. 发明授权

US06750095B1 Integrated circuit with vertical transistors 失效
标题翻译：集成电路与垂直晶体管
公开(公告)号：US06750095B1
公开(公告)日：2004-06-15
申请号：US09787966
申请日：2001-05-29
申请人： Emmerich Bertagnoll , Franz Hofmann , Bernd Goebel , Wolfgang Roesner
发明人： Emmerich Bertagnoll , Franz Hofmann , Bernd Goebel , Wolfgang Roesner
IPC分类号： H01L218242
CPC分类号： H01L27/10876 , H01L27/1052 , H01L27/10823 , H01L27/112 , H01L27/11273
摘要： A method of producing an integrated circuit having a vertical MOS transistor includes doping a substrate to form a layer adjacent to its surface and forming a lower doped layer serving as the transistor's first source/drain region. The transistor's channel region is formed by doping a central layer above the lower layer. A second source/drain region is formed by doping an upper layer above the central layer. The upper, central and lower layers form a layer sequence having opposed first and second faces. A connecting structure is formed on the first face to electrically connect the channel region and the substrate. The connecting structure laterally adjoins at least the central layer and the lower layer, and extends into the substrate. A gate dielectric and adjacent gate electrode are formed on the second face.
摘要翻译：制造具有垂直MOS晶体管的集成电路的方法包括：掺杂衬底以形成与其表面相邻的层，并形成用作晶体管的第一源极/漏极区的下掺杂层。晶体管的沟道区域通过在下层上掺杂中心层而形成。通过在中心层上方掺杂上层形成第二源/漏区。上层，中层和下层形成具有相对的第一和第二面的层序列。在第一面上形成连接结构，以电连接沟道区和衬底。连接结构至少横向邻接中心层和下层，并延伸到基底中。在第二面上形成栅电介质和相邻栅电极。

19. 发明授权

US06639269B1 Electrically programmable memory cell configuration and method for fabricating it 失效
标题翻译：电可编程存储单元配置及其制造方法
公开(公告)号：US06639269B1
公开(公告)日：2003-10-28
申请号：US09648952
申请日：2000-08-25
申请人： Franz Hofmann , Josef Willer
发明人： Franz Hofmann , Josef Willer
IPC分类号： H01L218247
CPC分类号： H01L27/11526 , H01L27/11546 , H01L29/42336 , H01L29/66825 , H01L29/7883
摘要： A memory cell contains a planar transistor whose channel region is disposed at a bottom of a depression in a substrate. A floating gate electrode of the transistor adjoins the bottom of the depression, the bottom being provided with a first dielectric disposed on sidewalls of the depression. Since the floating gate electrode has a larger area than the channel region, a capacitance formed by a control gate electrode applied on the floating gate electrode and the floating gate electrode is greater than a capacitance formed by the floating gate electrode and the channel region. Two source/drain regions of the transistor likewise adjoin the sidewalls of the depression. An insulation, which is thicker than the first dielectric, isolates the floating gate electrode from the source/drain regions, so that the source/drain regions do not contribute to the coupling ratio.
摘要翻译：存储单元包含平面晶体管，其沟道区设置在衬底中的凹陷的底部。晶体管的浮置栅电极邻接凹陷的底部，底部设置有设置在凹陷的侧壁上的第一电介质。由于浮栅电极具有比沟道区更大的面积，所以由施加在浮置栅电极和浮置栅电极上的控制栅电极形成的电容大于由浮栅电极和沟道区形成的电容。晶体管的两个源极/漏极区同样邻接凹陷的侧壁。比第一电介质厚的绝缘体将浮置栅极与源极/漏极区隔离，使得源极/漏极区域对耦合比没有贡献。

20. 发明授权

US06475866B2 Method for production of a memory cell arrangement 失效
标题翻译：存储单元布置的制造方法
公开(公告)号：US06475866B2
公开(公告)日：2002-11-05
申请号：US09774316
申请日：2001-01-31
申请人： Franz Hofmann , Wolfgang Krautschneider , Josef Willer
发明人： Franz Hofmann , Wolfgang Krautschneider , Josef Willer
IPC分类号： H01L21336
CPC分类号： H01L27/112 , G11C11/5692 , H01L27/11273
摘要： A method for production of a memory cell arrangement which includes vertical MOS transistors as memory cells, wherein the information is stored utilizing at least three different threshold voltage values of the transistors by multi-level programming. One threshold voltage value is realised by the thickness of the gate dielectric in the sense of a thick oxide transistor and the other threshold voltage values are realised by different channel dopings. The arrangement can be produced with as area requirement for each memory cell of 2 F2 (F: minimum structure size).
摘要翻译：一种用于生产包括垂直MOS晶体管作为存储单元的存储单元布置的方法，其中通过多级编程利用晶体管的至少三个不同阈值电压值存储信息。通过厚氧化物晶体管的意义上的栅极电介质的厚度实现一个阈值电压值，并且通过不同的沟道掺杂实现其它阈值电压值。可以按照2 F2（F：最小结构尺寸）的每个存储单元的面积要求来生成该布置。

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