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11. 发明授权

US06534871B2 Device including an epitaxial nickel silicide on (100) Si or stable nickel silicide on amorphous Si and a method of fabricating the same 失效
公开(公告)号：US06534871B2
公开(公告)日：2003-03-18
申请号：US09855391
申请日：2001-05-14
申请人： Jer-shen Maa , Douglas J. Tweet , Yoshi Ono , Fengyan Zhang , Sheng Teng Hsu
发明人： Jer-shen Maa , Douglas J. Tweet , Yoshi Ono , Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L2348
CPC分类号： H01L21/28518 , H01L29/456
摘要： An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.

12. 发明授权

US07256429B2 Memory cell with buffered-layer 有权
标题翻译：带缓冲层的存储单元
公开(公告)号：US07256429B2
公开(公告)日：2007-08-14
申请号：US11314222
申请日：2005-12-21
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang , Wei Pan , Wei-Wei Zhuang , David R. Evans , Masayuki Tajiri
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7−X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1−XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.
摘要翻译：提供了一种用于形成缓冲层存储单元的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域和0.6，厚度在10至200nm的范围内。

13. 发明授权

US07402456B2 PCMO thin film with memory resistance properties 有权
标题翻译：具有记忆电阻特性的PCMO薄膜
公开(公告)号：US07402456B2
公开(公告)日：2008-07-22
申请号：US10831677
申请日：2004-04-23
申请人： Wei-Wei Zhuang , Tingkai Li , Sheng Teng Hsu , Fengyan Zhang
发明人： Wei-Wei Zhuang , Tingkai Li , Sheng Teng Hsu , Fengyan Zhang
IPC分类号： H01L21/44
CPC分类号： H01L45/04 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2213/31 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method is provided for forming a Pr0.3Ca0.7MnO3 (PCMO) thin film with crystalline structure-related memory resistance properties. The method comprises: forming a PCMO thin film with a first crystalline structure; and, changing the resistance state of the PCMO film using pulse polarities responsive to the first crystalline structure. In one aspect the first crystalline structure is either amorphous or a weak-crystalline. Then, the resistance state of the PCMO film is changed in response to unipolar pulses. In another aspect, the PCMO thin film has either a polycrystalline structure. Then, the resistance state of the PCMO film changes in response to bipolar pulses.
摘要翻译：提供了一种用于形成具有结晶结构相关的记忆电阻性质的Pr 0.3M 3 Ca 0.7 MnO 3（PCMO）薄膜的方法。该方法包括：形成具有第一晶体结构的PCMO薄膜; 并且使用响应于第一晶体结构的脉冲极性来改变PCMO膜的电阻状态。在一个方面，第一晶体结构是无定形或弱结晶。然后，响应于单极脉冲改变PCMO膜的电阻状态。另一方面，PCMO薄膜具有多晶结构。然后，PCMO膜的电阻状态响应于双极性脉冲而改变。

14. 发明授权

US06762063B2 Method of fabricating non-volatile ferroelectric transistors 有权
标题翻译：制造非易失性铁电晶体管的方法
公开(公告)号：US06762063B2
公开(公告)日：2004-07-13
申请号：US10395368
申请日：2003-03-24
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： H01L2100
CPC分类号： H01L29/6684 , H01L21/28291 , H01L29/78391
摘要： A method of fabricating a non-volatile ferroelectric memory transistor includes forming a bottom electrode; depositing a ferroelectric layer over an active region beyond the margins of the bottom electrode; depositing a top electrode on the ferroelectric layer; and metallizing the structure to form a source electrode, a gate electrode and a drain electrode. A non-volatile ferroelectric memory transistor includes a bottom electrode formed above a gate region, wherein the bottom electrode has a predetermined area within a peripheral boundary; a ferroelectric layer extending over and beyond the bottom electrode peripheral boundary; and a top electrode formed on said ferroelectric layer.
摘要翻译：制造非挥发性铁电存储晶体管的方法包括：形成底电极; 在超过底部电极的边缘的有源区域上沉积铁电层; 在铁电层上沉积顶部电极; 并且将该结构金属化以形成源电极，栅电极和漏电极。非挥发性铁电存储晶体管包括形成在栅极区域上方的底部电极，其中底部电极在外围边界内具有预定区域; 延伸超过底部电极周边边界的铁电层; 以及形成在所述铁电层上的顶部电极。

15. 发明授权

US06673664B2 Method of making a self-aligned ferroelectric memory transistor 失效
标题翻译：制造自对准铁电存储晶体管的方法
公开(公告)号：US06673664B2
公开(公告)日：2004-01-06
申请号：US09978487
申请日：2001-10-16
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang
IPC分类号： H01L218238
CPC分类号： H01L29/51 , H01L21/28291 , H01L21/31691 , H01L27/11502 , H01L27/11507 , H01L29/516
摘要： A method of making a self-aligned ferroelectric memory transistor includes preparing a substrate, shallow trench isolation, n the polysilicon; and forming a gate stack, including: depositing a layer of silicon nitride; selectively etching the silicon nitride, the bottom electrode and the polysilicon; selectively etching the polysilicon to the level of the first dielectric layer; and implanting and activating ions to form a source region and a drain region; forming a sidewall barrier layer; depositing a layer of ferroelectric material; forming a top electrode structure on the ferroelectric material; and finishing the structure, including passivation, oxide depositing and metallization.
摘要翻译：制造自对准铁电存储晶体管的方法包括制备衬底，浅沟槽隔离，n多晶硅; 以及形成栅叠层，包括：沉积氮化硅层; 选择性地蚀刻氮化硅，底部电极和多晶硅; 选择性地将多晶硅蚀刻到第一介电层的水平面; 以及植入和激活离子以形成源区和漏区; 形成侧壁阻挡层; 沉积一层铁电材料; 在铁电材料上形成顶部电极结构; 并完成结构，包括钝化，氧化物沉积和金属化。

16. 发明授权

US07379320B2 Method for operating an MFIS ferroelectric memory array 有权
标题翻译：用于操作MFIS铁电存储器阵列的方法
公开(公告)号：US07379320B2
公开(公告)日：2008-05-27
申请号：US11262117
申请日：2005-10-28
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： G11C11/22 , H01L21/8246 , H01L21/8247
CPC分类号： H01L27/1159 , H01L21/84 , H01L27/11502 , H01L27/11585
摘要： An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.
摘要翻译：一种MFIS存储器阵列，具有多个具有连接多个MFIS存储晶体管栅极的字线的MFIS存储晶体管，其中连接到公共字线的所有MFIS存储晶体管具有公共源，每个晶体管漏极用作位输出，以及沿着字线的所有MFIS通道被P +区隔开，并且通过P +区进一步连接到SOI衬底上的P +衬底区域。还提供了在SOI衬底上制造MFIS存储器阵列的方法; 执行一个或多个字线的块擦除的方法以及有选择地编程位的方法。

17. 发明授权

US06819583B2 Ferroelectric resistor non-volatile memory array 失效
标题翻译：铁电电阻非易失性存储器阵列
公开(公告)号：US06819583B2
公开(公告)日：2004-11-16
申请号：US10345726
申请日：2003-01-15
申请人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang
发明人： Sheng Teng Hsu , Tingkai Li , Fengyan Zhang
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric thin film resistor memory array is formed on a substrate and includes plural memory cells arranged in an array of rows and columns; wherein each memory cell includes: a FE resistor having a pair of terminals, and a transistor associated with each resistor, wherein each transistor has a gate, a drain and a source, and wherein the drain of each transistor is electrically connected to one terminal of its associated resistor; a word line connected to the gate of each transistor in a row; a programming line connected to each memory cell in a column; and a bit line connected to each memory cell in a column.
摘要翻译：铁基薄膜电阻存储阵列形成在基板上，并且包括以行和列为阵列排列的多个存储单元; 其中每个存储器单元包括：具有一对端子的FE电阻器和与每个电阻器相关联的晶体管，其中每个晶体管具有栅极，漏极和源极，并且其中每个晶体管的漏极电连接到其相关电阻器; 连接到每个晶体管的栅极的字线; 连接到列中的每个存储单元的编程线; 以及连接到列中每个存储单元的位线。

18. 发明授权

US06759250B2 Deposition method for lead germanate ferroelectric structure with multi-layered electrode 失效
标题翻译：具有多层电极的锗酸铅铁电结构沉积方法
公开(公告)号：US06759250B2
公开(公告)日：2004-07-06
申请号：US10196503
申请日：2002-07-15
申请人： Fengyan Zhang , Tingkai Li , Sheng Teng Hsu
发明人： Fengyan Zhang , Tingkai Li , Sheng Teng Hsu
IPC分类号： H01L2100
CPC分类号： H01L28/56 , H01L21/31604 , H01L21/31691 , H01L28/75
摘要： The ferroelectric structure including a Pt/Ir layered electrode used in conjunction with a lead germanate (Pb5Ge3O11) thin film is provided. The electrode exhibits good adhesion to the substrate, and barrier properties resistant to oxygen and lead. Ferroelectric properties are improved, without detriment to the leakage current, by using a thin IrO2 layer formed in situ, during the MOCVD lead germanate (Pb5Ge3O11) thin film process. By using a Pt/Ir electrode, a relatively low MOCVD processing temperature is required to achieve c-axis oriented lead germanate (Pb5Ge3O11) thin film. The temperature range of MOCVD c-axis oriented lead germanate (Pb5Ge3O11) thin film on top of Pt/Ir is 400-500° C. Further, a relatively large nucleation density is obtained, as compared to using single-layer iridium electrode. Therefore, the lead germanate (Pb5Ge3O11) thin film has a smooth surface, a homogeneous microstructure, and homogeneous ferroelectric properties. A method of forming the above-mentioned multi-layered electrode ferroelectric structure is also provided.
摘要翻译：提供了包括与锗酸铅（Pb5Ge3O11）薄膜结合使用的Pt / Ir层叠电极的铁电体结构。该电极对基材表现出良好的粘合性，并且对氧和铅具有阻挡性能。在MOCVD锗酸铅（Pb5Ge3O11）薄膜工艺中，通过使用在原位形成的薄的IrO 2层，铁电性能得到改善，而不损害漏电流。通过使用Pt / Ir电极，需要相对低的MOCVD处理温度来实现c轴取向的锗酸铅（Pb5Ge3O11）薄膜。 Pt / Ir顶部的MOCVD c轴取向锗酸铅（Pb5Ge3O11）薄膜的温度范围为400-500℃。与使用单层铱电极相比，获得了较大的成核密度。因此，锗酸铅（Pb5Ge3O11）薄膜表面光滑，微观组织均匀，铁电性能均匀。还提供了形成上述多层电极铁电体结构体的方法。

19. 发明授权

US06531324B2 MFOS memory transistor & method of fabricating same 失效
公开(公告)号：US06531324B2
公开(公告)日：2003-03-11
申请号：US09820039
申请日：2001-03-28
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： H01L2100
CPC分类号： H01L29/516 , H01L21/28291 , H01L29/78391
摘要： A ferroelectric transistor gate structure with a ferroelectric gate and passivation sidewalls is provided. The passivation sidewalls serve as an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing passivation insulator material, etching the passivation insulator material using anisotropic plasma etching to form passivation sidewalls, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.

20. 发明授权

US07112837B2 MFIS ferroelectric memory array 有权
标题翻译： MFIS铁电存储器阵列
公开(公告)号：US07112837B2
公开(公告)日：2006-09-26
申请号：US11262545
申请日：2005-10-28
申请人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
发明人： Sheng Teng Hsu , Fengyan Zhang , Tingkai Li
IPC分类号： H01L29/76
CPC分类号： H01L27/1159 , H01L21/84 , H01L27/11502 , H01L27/11585
摘要： An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.
摘要翻译：一种MFIS存储器阵列，具有多个具有连接多个MFIS存储晶体管栅极的字线的MFIS存储晶体管，其中连接到公共字线的所有MFIS存储晶体管具有公共源，每个晶体管漏极用作位输出，以及沿着字线的所有MFIS通道被P +区隔开，并且通过P +区进一步连接到SOI衬底上的P +衬底区域。还提供了在SOI衬底上制造MFIS存储器阵列的方法; 执行一个或多个字线的块擦除的方法以及有选择地编程位的方法。

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