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    • 16. 发明授权
    • Digital data processing system incorporating apparatus for resolving
names
    • 数字数据处理系统,包括解析名称的装置
    • US4661903A
    • 1987-04-28
    • US647271
    • 1984-09-04
    • Walter A. Wallach, Jr.Michael S. RichmondJohn K. AhlstromDavid H. BernsteinRichard G. Bratt
    • Walter A. Wallach, Jr.Michael S. RichmondJohn K. AhlstromDavid H. BernsteinRichard G. Bratt
    • G06F9/318G06F9/35G06F9/44G06F13/00
    • G06F9/30192G06F9/35G06F9/4428
    • Apparatus in a digital computer system for obtaining descriptors of data from names representing the data. The digital computer system executes sequences of instructions. Names representing data processed during execution of an instruction sequence are associated with the instruction sequence. Each name associated with the instruction sequence corresponds to a name table entry associated with the instruction sequence. The operation of resolving a name, i.e., obtaining the descriptor for the data represented by the name, is performed by name processing apparatus in processors of the data processing system. In response to a name, the name processing apparatus locates the name table entry corresponding to the name obtains the descriptor for the item represented by the name using the information in the name table entry corresponding to the name. In a present embodiment, the descriptor specifies the address and length of a data item. The information in the name table entry specifies the address of the represented item by specifying a base address and a displacement and further specifies the length and type of the represented item.
    • 数字计算机系统中的装置,用于从表示数据的名称获得数据的描述符。 数字计算机系统执行指令序列。 表示在执行指令序列期间处理的数据的名称与指令序列相关联。 与指令序列相关联的每个名称对应于与指令序列相关联的名称表条目。 通过名称处理装置在数据处理系统的处理器中执行解析名称的操作,即获得由名称表示的数据的描述符。 响应于名称,名称处理设备找到与名称相对应的名称表项,使用与名称相对应的名称表项中的信息来获得由名称表示的项目的描述符。 在本实施例中,描述符指定数据项的地址和长度。 名称表项目中的信息通过指定基址和位移来指定所表示项目的地址,并进一步指定所表示项目的长度和类型。
    • 19. 发明授权
    • Data processing system
    • 数据处理系统
    • US4649470A
    • 1987-03-10
    • US435385
    • 1982-10-20
    • David H. BernsteinEdward M. BuckleyRoger W. MarchRonald I. Gusowski, deceased
    • David H. BernsteinEdward M. BuckleyRoger W. MarchRonald I. Gusowski, deceased
    • G06F9/26G06F13/36G06F13/42H03K23/66G06F13/38
    • H03K23/667G06F13/36G06F13/4217G06F9/26
    • A data processing system using microcode architecture in which a two-level microcode system comprises one or more first, or "horizontal", microinstructions and a plurality of second, or "vertical", microinstruction portions in a vertical microcontrol store. In a preferred embodiment the vertical microinstruction portions include one or more "modifier" fields, a selection field for selecting a horizontal microinstruction and a sequencing field for selecting the next vertical microinstruction portion of a sequence thereof, one or more fields of the horizontal microinstructions being capable of modification by the vertical modifier fields in order to form output microinstructions for performing data processing operations. Unique bus protocol signals are generated to prevent simultaneous access to the system bus by two competing system components and to permit substantially immediate control of the systems bus by a component without requiring a CPU decision thereon. Further, a unique system I/O interface unit permits access to certain I/O components via other I/O buses, such unit utilizing a unique polling technique to identify on an updated basis, all components present on one of such other buses. The system I/O interface unit also includes a unique frequency synthesizer unit for providing at least one clock signal having a substantially constant frequency which can be generated in response to any one of a plurality of input clock signals each having a different frequency.
    • 一种使用微代码架构的数据处理系统,其中两级微代码系统包括垂直微控制器存储器中的一个或多个第一或“水平”微指令以及多个第二或“垂直”微指令部分。 在优选实施例中,垂直微指令部分包括一个或多个“修改器”字段,用于选择水平微指令的选择字段和用于选择其序列的下一垂直微指令部分的测序字段,水平微指令的一个或多个字段为 能够通过垂直修改器字段进行修改,以便形成用于执行数据处理操作的输出微指令。 产生独特的总线协议信号以防止由两个竞争的系统组件同时访问系统总线,并允许由组件基本上立即控制系统总线,而不需要CPU决定。 此外,独特的系统I / O接口单元允许通过其他I / O总线访问某些I / O组件,这种单元利用独特的轮询技术,以更新的方式识别存在于其中一个其它总线上的所有组件。 系统I / O接口单元还包括唯一的频率合成器单元,用于提供至少一个具有基本上恒定频率的时钟信号,该时钟信号可以响应于具有不同频率的多个输入时钟信号中的任何一个而产生。