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11. 发明授权

US08316284B2 Collecting failure information on error correction code (ECC) protected data 有权
标题翻译：收集有关纠错码（ECC）保护数据的故障信息
公开(公告)号：US08316284B2
公开(公告)日：2012-11-20
申请号：US12360402
申请日：2009-01-27
申请人： Arthur J. O'Neill , Patrick J. Meaney
发明人： Arthur J. O'Neill , Patrick J. Meaney
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F11/10
摘要： Methods of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug.
摘要翻译：纠错码（ECC）调试方法可以包括检测是否发生位错误; 确定哪些位或位是错误的; 并使用位错误信息进行调试。该方法还可以包括比较ECC综合征与一个或多个ECC综合征模式。该方法可以允许累积位错误信息，将错误位故障与模式进行比较，捕获数据，计数错误，确定拾取/丢弃信息或停止机器进行调试。

12. 发明申请

US20090164874A1 Collecting Failure Information On Error Correction Code (ECC) Protected Data 有权
标题翻译：收集有关错误纠正码（ECC）受保护数据的故障信息
公开(公告)号：US20090164874A1
公开(公告)日：2009-06-25
申请号：US12360402
申请日：2009-01-27
申请人： Arthur J. O'Neill , Patrick J. Meaney
发明人： Arthur J. O'Neill , Patrick J. Meaney
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： G06F11/10
摘要： Methods and means of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The method may allow for accumulating bit error information, comparing error bit failures against a pattern, trapping data, counting errors, determining pick/drop information, or stopping the machine for debug.
摘要翻译：纠错码（ECC）调试的方法和手段可以包括检测是否发生位错误; 确定哪些位或位是错误的; 并使用位错误信息进行调试。该方法还可以包括比较ECC综合征与一个或多个ECC综合征模式。该方法可以允许累积位错误信息，将错误位故障与模式进行比较，捕获数据，计数错误，确定拾取/丢弃信息或停止机器进行调试。

13. 发明申请

US20130339822A1 BAD WORDLINE/ARRAY DETECTION IN MEMORY 有权
公开(公告)号：US20130339822A1
公开(公告)日：2013-12-19
申请号：US13523971
申请日：2012-06-15
申请人： Patrick J. Meaney , Arthur J. O'Neill , Gary E. Strait
发明人： Patrick J. Meaney , Arthur J. O'Neill , Gary E. Strait
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/05 , G06F11/073 , G06F11/1008 , G06F11/1064 , G06F11/1666 , G06F11/20
摘要： A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline. The controller determines that the wordline is a failing wordline based on detecting the first error in the first ECC word and the second error in the second ECC word.

14. 发明申请

US20070300095A1 Double Data Rate Chaining for Synchronous DDR Interfaces 失效
标题翻译：双数据速率链接同步DDR接口
公开(公告)号：US20070300095A1
公开(公告)日：2007-12-27
申请号：US11426651
申请日：2006-06-27
申请人： Michael Fee , Patrick J. Meaney , Christopher J. Berry , Jonathan Y. Chen , Alan P. Wagstaff
发明人： Michael Fee , Patrick J. Meaney , Christopher J. Berry , Jonathan Y. Chen , Alan P. Wagstaff
IPC分类号： G06F1/12
CPC分类号： G06F13/4217
摘要： A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.
摘要翻译：一种系统和方法，其中接收芯片分别锁存从双数据速率总线接收的数据的每一半。每一半都可以立即启动; 一个在正常的芯片周期时间，另一个从主（L1）锁存器半个周期启动到正常的芯片周期时间。首先推出的一半数据通过芯片沿其标准设计芯片路径进行，由芯片驱动接口锁存器捕获，并在芯片上的一个延迟周期后再次启动。数据的后半部分通过芯片在上半部分后半个周期进行，并且稍后通过进入从（L2）锁存器的路径被锁存半个时钟周期。在本地时钟的下一个边缘，数据然后从L2锁存器继续到驱动双数据速率接口。这允许半周期的半周期设置时间，以便可以再次启动，在芯片上保持一个周期的时间。

15. 发明授权

US07484023B2 Computer system apparatus for stabilizing asynchronous interfaces 失效
标题翻译：用于稳定异步接口的计算机系统装置
公开(公告)号：US07484023B2
公开(公告)日：2009-01-27
申请号：US11532199
申请日：2006-09-15
申请人： Patrick J. Meaney , Anthony P. Cullen , Michael Fee
发明人： Patrick J. Meaney , Anthony P. Cullen , Michael Fee
IPC分类号： G06F13/42 , H03K19/00 , G06F13/14
CPC分类号： G06F13/4226
摘要： A computer system apparatus for asynchronous data transfer between a source and sink without the use of an asynchronous control signal. includes metastability circuits, data change detection logic, a stability window delay counter, and a mux/register pair to allow for the holding of previous stable data during the transition. While the processing logic employed specifically applies to asynchronous logic, the logic can be extended to synchronous or untimed interfaces as well. Also disclosed is a programmable means to adjust the window delay.
摘要翻译：一种用于在不使用异步控制信号的情况下在源和汇之间进行异步数据传输的计算机系统装置。包括亚稳态电路，数据变化检测逻辑，稳定窗口延迟计数器和多路复用器/寄存器对，以允许在转换期间保持先前的稳定数据。虽然采用的处理逻辑专门适用于异步逻辑，但逻辑也可以扩展到同步或未定义的接口。还公开了一种用于调整窗口延迟的可编程装置。

16. 发明申请

US20070300096A1 Late Data Launch for a Double Data Rate Elastic Interface 失效
标题翻译：延迟数据启动双数据速率弹性接口
公开(公告)号：US20070300096A1
公开(公告)日：2007-12-27
申请号：US11426671
申请日：2006-06-27
申请人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
发明人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
IPC分类号： G06F1/12
CPC分类号： G06F13/4059
摘要： A double data rate interface in which the set-up interval is extended for a data path in which data is delayed relative to the other data path. Data is latched into a register comprised of mid cycle type latches, such as for example L2* latches. For example, if the delayed half of the data is not available until the second half of the double data rate cycle, the second half of the data is allowed to have a set-up interval around the mid cycle point while the on-chip timing logic launches the least delayed half of the data on the clock edge after it is set up, without waiting for the expiration of the set up interval of the delayed data.
摘要翻译：双数据速率接口，其中针对数据相对于另一数据路径延迟数据路径的设置间隔进行扩展。数据被锁存到由中间循环型锁存器组成的寄存器中，例如L2 *锁存器。例如，如果延迟的一半数据在双倍数据速率周期的下半部分之前不可用，则数据的后半部分被允许具有围绕中间周期点的建立间隔，同时片内定时在建立之后，逻辑在时钟沿启动最少延迟的一半数据，而不用等待延迟数据的设置间隔的到期。

17. 发明申请

US20070300032A1 Early Directory Access of A Double Data Rate Elastic Interface 失效
标题翻译：双数据速率弹性接口的早期目录访问
公开(公告)号：US20070300032A1
公开(公告)日：2007-12-27
申请号：US11426675
申请日：2006-06-27
申请人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
发明人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
IPC分类号： G06F13/00
CPC分类号： G06F13/4059 , G06F12/0855 , G06F12/0864
摘要： A system and method to organize and use data sent over a double data rate interface so that the system operation does not experience a time penalty. The first cycle of data is used independently of the second cycle so that latency is not jeopardized. There are many applications. In a preferred embodiment for an L2 cache, the system transmits congruence class data in the first half and can start to access the L2 cache directory with the congruence class data.
摘要翻译：一种用于组织和使用通过双数据速率接口发送的数据的系统和方法，使得系统操作不会经历时间惩罚。数据的第一个循环独立于第二个周期使用，以便等待时间不会受到损害。有很多应用程序。在L2高速缓存的优选实施例中，系统在前半部分发送同余类数据，并且可以开始以一致类数据访问L2高速缓存目录。

18. 发明授权

US07739538B2 Double data rate chaining for synchronous DDR interfaces 失效
标题翻译：双数据速率链接同步DDR接口
公开(公告)号：US07739538B2
公开(公告)日：2010-06-15
申请号：US11426651
申请日：2006-06-27
申请人： Michael Fee , Patrick J. Meaney , Christopher J. Berry , Jonathan Y. Chen , Alan P. Wagstaff
发明人： Michael Fee , Patrick J. Meaney , Christopher J. Berry , Jonathan Y. Chen , Alan P. Wagstaff
IPC分类号： G06F5/06 , G11C8/16
CPC分类号： G06F13/4217
摘要： A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.
摘要翻译：一种系统和方法，其中接收芯片分别锁存从双数据速率总线接收的数据的每一半。每一半都可以立即启动; 一个在正常的芯片周期时间，另一个从主（L1）锁存器半个周期启动到正常的芯片周期时间。首先推出的一半数据通过芯片沿其标准设计芯片路径进行，由芯片驱动接口锁存器捕获，并在芯片上的一个延迟周期后再次启动。数据的后半部分通过芯片在上半部分后半个周期进行，并且稍后通过进入从（L2）锁存器的路径被锁存半个时钟周期。在本地时钟的下一个边缘，数据然后从L2锁存器继续到驱动双数据速率接口。这允许半周期的半周期设置时间，以便可以再次启动，在芯片上保持一个周期的时间。

19. 发明申请

US20070300040A1 Method for Resource Sharing in a Multiple Pipeline Environment 有权
标题翻译：多管道环境资源共享方法
公开(公告)号：US20070300040A1
公开(公告)日：2007-12-27
申请号：US11425398
申请日：2006-06-21
申请人： Patrick J. Meaney , Michael Fee , Christopher M. Carney
发明人： Patrick J. Meaney , Michael Fee , Christopher M. Carney
IPC分类号： G06F15/00 , G06F13/14
CPC分类号： G06F13/37
摘要： Disclosed is a method and apparatus for arbitration between multiple pipelines over shared resources for an SMP computer system. The computer includes logic to defer arbitration until later in the pipeline to help reduce latency to each pipeline. Also, introduced is the concept of retry tags for better priority to avoid lock-out. The system also includes round-robin tokens to manage rejected requests to allow better fairness on conflicts. While the processing logic employed specifically applies to cross-interrogation, the logic can be extended to other common resources. The illustrated SMP computer system also has self-correcting logic to maintain good round-robin tokens.
摘要翻译：公开了一种用于通过SMP计算机系统的共享资源在多个管线之间仲裁的方法和装置。该计算机包括延迟仲裁的逻辑，直到稍后的管道，以帮助减少每个管道的延迟。此外，引入了重试标签的概念，以便更好地优先避免锁定。该系统还包括循环令牌来管理被拒绝的请求，以使冲突更加公平。虽然采用的处理逻辑特别适用于交叉询问，但逻辑可以扩展到其他公共资源。所示的SMP计算机系统还具有自校正逻辑，以保持良好的循环令牌。

20. 发明授权

US07809874B2 Method for resource sharing in a multiple pipeline environment 有权
标题翻译：多管道环境中资源共享的方法
公开(公告)号：US07809874B2
公开(公告)日：2010-10-05
申请号：US11425398
申请日：2006-06-21
申请人： Patrick J. Meaney , Michael Fee , Christopher M. Carney
发明人： Patrick J. Meaney , Michael Fee , Christopher M. Carney
IPC分类号： G06F13/14
CPC分类号： G06F13/37
摘要： Disclosed is a method and apparatus for arbitration between multiple pipelines over shared resources for an SMP computer system. The computer includes logic to defer arbitration until later in the pipeline to help reduce latency to each pipeline. Also, introduced is the concept of retry tags for better priority to avoid lock-out. The system also includes round-robin tokens to manage rejected requests to allow better fairness on conflicts. While the processing logic employed specifically applies to cross-interrogation, the logic can be extended to other common resources. The illustrated SMP computer system also has self-correcting logic to maintain good round-robin tokens.
摘要翻译：公开了一种用于通过SMP计算机系统的共享资源在多个管线之间仲裁的方法和装置。该计算机包括延迟仲裁的逻辑，直到稍后的管道，以帮助减少每个管道的延迟。此外，引入了重试标签的概念，以便更好地优先避免锁定。该系统还包括循环令牌来管理被拒绝的请求，以使冲突更加公平。虽然采用的处理逻辑特别适用于交叉询问，但逻辑可以扩展到其他公共资源。所示的SMP计算机系统还具有自校正逻辑，以保持良好的循环令牌。

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